KM416C256D-5 Просмотр технического описания (PDF) - Samsung

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KM416C256D-5

256K x 16Bit CMOS Dynamic RAM with Fast Page Mode

Samsung 

KM416C256D, KM416V256D

CMOS DRAM

11. 512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L-

version).

12. tASC, tCAH are referenced to the earlier CAS rising edge.

13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

14. tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.

15. tCWL is specified from W falling edge to the earlier CAS rising edge.

16. tCSR is referenced to earlier CAS falling low before RAS transition low.

17. tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR

20. tDS, tDH are specified for earlier CAS falling low.

tCHR

LCAS

UCAS

DQ0 ~ DQ15

w

tDS

tDH

Din

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