K7R161884B Просмотр технического описания (PDF) - Samsung

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производитель

K7R161884B

18Mb QDRII SRAM Specification 165FBGA with Pb & Pb-Free

Samsung 

K7R163684B

K7R161884B

512Kx36 & 1Mx18 QDRTM II b4 SRAM

STATE DIAGRAM

POWER-UP

READ NOP

READ

WRITE

WRITE NOP

READ

READ

D count=2

LOAD NEW

READ ADDRESS

D count=0

ALWAYS

READ

D count=2

DDR READ

D count=D count+1

READ

D count=1

ALWAYS

INCREMENT

READ ADDRESS

WRITE

LOAD NEW

WRITE ADDRESS

D count=0

WRITE

D count=2

ALWAYS

WRITE

D count=2

DDR WRITE

D count=D count+1

ALWAYS

WRITE

D count=1

INCREMENT

WRITE ADDRESS

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. “READ” refers to read active status with R=Low, “READ” refers to read inactive status with R=high. “WRITE” and "WRITE" are the same case.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

Rev. 5.0 July 2006

-8-

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