K7R161884B-FC20(2004) Просмотр технического описания (PDF) - Samsung
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K7R161884B-FC20 Datasheet PDF : 18 Pages
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K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Storage Temperature
Operating Temperature
Storage Temperature Range Under Bias
SYMBOL
VDD
VDDQ
VIN
TSTG
TOPR
TBIAS
RATING
-0.5 to 2.9
-0.5 to VDD
-0.5 to VDD+0.3
-65 to 150
0 to 70
-10 to 85
UNIT
V
V
V
°C
°C
°C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTE
Input Leakage Current
IIL
VDD=Max ; VIN=VSS to VDDQ
-2
+2
µA
Output Leakage Current
IOL Output Disabled,
-2
+2
µA
-30
-
550
Operating Current
(x36) : DDR
ICC
VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-25
-20
-
-
500
mA 1,5
450
-16
400
-30
-
450
Operating Current
(x18) : DDR
ICC
VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-25
-20
-
-
400
mA 1,5
350
-16
300
-30
-
Device deselected,
-25
-
Standby Current(NOP): DDR
ISB1 IOUT=0mA, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V -20
-
-16
-
260
240
mA 1,6
220
200
Output High Voltage
VOH1
VDDQ/2-0.12
VDDQ/2+0.12
V 2,7
Output Low Voltage
VOL1
VDDQ/2-0.12
VDDQ/2+0.12
V 3,7
Output High Voltage
VOH2 IOH=-1.0mA
VDDQ-0.2
VDDQ
V
4
Output Low Voltage
VOL2 IOL=1.0mA
VSS
0.2
V
4
Input Low Voltage
VIL
-0.3
VREF-0.1
V 8,9
Input High Voltage
VIH
VREF+0.1
VDDQ+0.3
V 8,10
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
-9-
July. 2004
Rev 3.1
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