K6R1008C1A-I Просмотр технического описания (PDF) - Samsung
Номер в каталоге
Компоненты Описание
производитель
K6R1008C1A-I Datasheet PDF : 8 Pages
| |||
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
K6R1008C1A-12
Min
Max
12
-
8
-
0
-
8
-
8
-
12
-
0
-
0
6
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tDW
6
-
tDH
0
-
tOW
3
-
* The above parameters are also guaranteed at industrial temperature range.
K6R1008C1A-15
Min
Max
15
-
10
-
0
-
10
-
10
-
15
-
0
-
0
7
7
-
0
-
3
-
K6R1008C1A-20
Unit
Min
Max
20
-
ns
12
-
ns
0
-
ns
12
-
ns
12
-
ns
20
-
ns
0
-
ns
0
9
ns
9
-
ns
0
-
ns
3
-
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tRC
tAA
tOH
Previous Valid Data
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
ICC
Current
ISB
tRC
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tHZ(3,4,5)
Valid Data
tOHZ
tOH
tPD
50%
Rev 4.0
-5-
February 1998
Share Link: 