K6E0808C1E-C Просмотр технического описания (PDF) - Samsung

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Компоненты Описание

производитель

K6E0808C1E-C

32K x 8 Bit High-Speed CMOS Static RAM

Samsung 

K6E0808C1E-C/E-L, K6E0808C1E-I/E-P

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

OE

Data out

VCC

ICC

Current

ISB

tRC

tAA

tCO

tOE

tOLZ

tLZ(4,5)

tPU

50%

For Cisco

CMOS SRAM

tHZ(3,4,5)

tOHZ

Valid Data

tOH

tPD

50%

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL

levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

OE

CS

WE

Data in

Data out

tWC

tAW

tCW(3)

tWR(5)

tAS(4)

tWP(2)

High-Z

tOHZ(6)

tDW

tDH

Valid Data

High-Z(8)

-6-

Revision 2.0

Feburary 1999

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