ISPLSI5256VE Просмотр технического описания (PDF) - Lattice Semiconductor

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ISPLSI5256VE

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5256VE

Functional Block Diagram

Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option)

VCCIO

1TOE

I/O 1

I/O 2

I/O 3

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 32

I/O 33

I/O 34

I/O 35

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Global Routing Pool

(GRP)

Boundary

Scan

Interface

TDI

TDO

I/O 107

I/O 106

I/O 105

I/O 104

I/O 93

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 75

I/O 74

I/O 73

I/O 72

RESET

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine

which I/O is shared by package type.

Package Type

100 TQFP

128 TQFP

256 fpBGA

272 BGA

Multplexed Signals

1/O 44 / CLK2 I/O 49 / CLK 3

I/O 59 / CLK2 I/O 65 / CLK3

I/O 119 / CLK2 I/O 131 / CLK3

I/O 119 / CLK2 I/O 131 / CLK3

I/O 0 / TOE

I/O 0 / TOE

I/O 0 / TOE

I/O 0 / TOE

2

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