LX64EV-5F100I Просмотр технического описания (PDF) - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

ispGDX2 Family Data Sheet

N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adja-

cent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output

clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay fea-

ture that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better per-

formance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL

Design and Usage Guidelines.

Figure 6. sysCLOCK PLL

PLL_LOCK

CLK_OUT

CLK_IN

PLL_RST

PLL_FBK

Input Clock

(M) Divider

1 to 32

Programmable

+Delay

--------------------

Programmable

-Delay

PLL (n)

Post-scalar

(V) Divider

1, 2, 4, 8,

16, 32

Feedback

Divider (N)

X 1 to 32

Clock (K)

Divider

2, 4, 8,

16, 32

Clock Net

To Adjacent_PLL

From

Adjacent_PLL

There are four global clock networks routed to each MRB block. These global clocks, CLK0-3, can either be gener-

ated by the PLL circuits or supplied externally. External clock pins can be configured as single-ended or differential

(LVDS) input. Figure 7 illustrates how the sysCLOCK PLL inputs and outputs can be routed to the I/O pins or gen-

eral routing. Figure 10 shows the clock network for the ispGDX2-256 and Figure 8 shows the clock networks for

ispGDX2-128 and ispGDX2-64. The Reset (0) pin from the Control Array of selected GDX Blocks can be pro-

grammed to reset the M Divider of the PLLs. This provides a means for generating the reset signal internally.

Table 5 details which GDX Block provides reset to the PLLs.

Table 5. Internal Reset Input of the PLL (M Divider)

ispGDX2-256

ispGDX2-128

ispGDX2-64

PLL0

GDX Block 5A

GDX Block 2A

GDX Block 0A

PLL1

GDX Block 7B

—

—

PLL2

GDX Block 1A

GDX Block 0A

GDX Block 1B

PLL3

GDX Block 3B

—

—

10

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