Philips Semiconductors
Power amplifier controller for GSM and
PCN systems
Preliminary specification
PCF5077T
TIMING CHARACTERISTICS
VDDA1, VDDA2 and VDDD = 2.7 to 6.0 V; VDDD = VDDA1 ≤ VDDA2; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
UNIT
Controller timing; see Fig.3
td(TRIG-B)
td(B-C)
td(TRIG-E)
td(E-G)
delay from positive TRIG edge to time B = 13⁄6Tcy
delay from time B to time C = 18Tcy
delay from negative TRIG edge to time E = 13⁄6Tcy
delay from time E to time G = 38Tcy
Serial bus timing; see Fig.6
−
1.0
µs
−
8.31
µs
−
1.0
µs
−
17.54
µs
SERIAL PROGRAMMING CLOCK (PIN CLK)
tr
rise time
tf
fall time
Tcy
clock period
ENABLE PROGRAMMING (PIN STROBE)
tstart
strobe start time to first clock edge
tend
strobe end time after last clock edge
REGISTER SERIAL INPUT DATA (PIN DATA)
tsu
input data to CLK set-up time
th
input data to CLK hold time
−
10
ns
−
10
ns
100
−
ns
0
−
ns
40
−
ns
20
−
ns
20
−
ns
handbook, full pagewidth
CLK
DATA
tsu
Tcy
th
MSB
STROBE
tstart
LSB
tend
MGK913
1997 Nov 19
Fig.6 Serial bus timing diagram.
14