Philips Semiconductors
Power amplifier controller for GSM and
PCN systems
Preliminary specification
PCF5077T
DC CHARACTERISTICS
VDDA1, VDDA2 and VDDD = VDD = 2.7 to 6.0 V; VDDD = VDDA1 ≤ VDDA2; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
VDDD
digital supply voltage
2.7
3.0
VDDA1
analog supply voltage 1
2.7
3.0
VDDA2
analog supply voltage 2
2.7
5.0
IDD(oper)(tot) total operating current on the VDD pins fCLK13 = 13 MHz; see Fig.5 −
9
IDD(idle)(tot) total idle current on the VDD pins
PD = LOW
−
4
Logic inputs (pins TRIG, STROBE, CLK and DATA)
ILIL
LOW-level input leakage current
VIL = 0 V
ILIH
HIGH-level input leakage current
VIH = 6 V
Ci
input capacitance
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
−5
−
−5
−
−
10
0
−
0.5VDD −
3-state output (pin DF)
VOL
LOW-state output voltage
VOH
HIGH-state output voltage
ILO
3-state output leakage current
IOL = IOH = 3 mA
IOL = IOH = 3 mA
VDF = 0 to VDD
−
−
0.7VDD −
−5
−
Low-swing master clock input (pin CLK13)
ILl
Ci
Zi
Vi(p−p)
input leakage current
input capacitance
input impedance
input voltage (peak-to-peak value)
fCLK13 = 13 MHz; note 1
note 2
−5
−
−
10
−
5
0.35 −
Sensor input voltage (pin VS)
Vi(VS)
input voltage at pin VS
−3.0 −
Band gap
Ibias
bias current (source for D1)
Vref
reference voltage
TC
temperature coefficient for Vref
tpu
power-up time for Vref
VVS = 0 V; Tamb = 25 °C;
TC = −0.08 µA/K
Tamb = 25 °C
note 3
21
1.18
−
−
28
1.25
±170
5
Power-on reset, threshold voltage Vth; see Fig.4
Vth
threshold voltage
trst
reset time
Tamb = 25 °C;
TC = −4 mV/K
1.2
1.5
−
−
MAX.
6.0
6.0
6.0
18
20
UNIT
V
V
V
mA
µA
+5
µA
+5
µA
−
pF
0.2VDD V
VDD
V
0.4
V
−
V
+5
µA
+5
µA
−
pF
−
kΩ
VDD
V
VDD
V
35
µA
1.32 V
−
ppm/K
50
µs
1.8
V
50
µs
Notes
1. An AC coupling with 33 pF is recommended.
2. Tested at nominal working condition (VDDD = VDDA1 = 3 V; VDDA2 = 5 V). AC coupling = 33 pF.
3. The necessary start-up time tON = 200 µs (see Fig.3) between PD and TRIG is more than tpu.
1997 Nov 19
12