TDA9816M Просмотр технического описания (PDF) - Philips Electronics

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TDA9816M

Multistandard multimedia IF-PLL and FM radio demodulator

Philips Electronics 

Philips Semiconductors

Multistandard multimedia IF-PLL and FM

radio demodulator

Preliminary specification

TDA9816M

The radio Automatic Frequency Control (AFC) stage is

comprised of a 10.7 MHz phase shifting network, a phase

detector (quadrature demodulator), a differential amplifier

input stage (which receives the limiting amplifier output

signal), and a current mode output stage.

A ceramic resonator is used for phase shifting. This

permits alignment-free operation.

AF signal processing

The AF signal processing stage consists of a pre-amplifier

for the FM-PLL demodulator output signal, an AF source

selector, a soft and forced mute stage with an integrated

time constant, and an AF post-amplifier.

The FM demodulator output signal is pre-amplified by an

operational amplifier (30 dB gain) with internal feedback,

high gain and high common mode rejection. The feedback

circuit, together with external capacitor CDEC connected to

pin 13, keeps the DC level at the pre-amplifier output

constant (2.3 V). An external resistor connected in series

with CDEC provides a gain-reduction capability.

The low-pass filter characteristic (130 kHz bandwidth) of

the amplifier reduces the harmonics of the IF signal at the

sound signal output.

The source selector operational amplifier selects and

amplifies the appropriate AF source signal by means of the

control logic: AM from the AM demodulator in TV L/L

accent mode, FM from the FM demodulator via

de-emphasis (internal resistor, external capacitor Cde-em at

pin 12) in TV B/G mode or FM direct from the FM

demodulator in radio mode.

Soft mute occurs when the internal level detector output

voltage is lower than the mute threshold voltage at pin 11

(provided an external resistor is not connected between

the limiter input, pin 15, and the supply voltage). The mute

stage reduces the AF signal by 25 dB, with an internal time

constant of approximately 7 ms.

If forced mute is active (see Table 2), or a resistor is

connected between pin 15 and ground, the mute stage will

reduce the AF signal level by more than 70 dB, with the

same time constant.

Otherwise, the AF signal level will not be reduced.

The AF post-amplifier, which was designed to include a

rail-to-rail output stage, provides the required AF output

level at pin 10.

Internal voltage stabilizer

The band gap circuit generates a voltage of approximately

1.25 V internally, independent of supply voltage and

temperature. A voltage regulator circuit connected to this

voltage generates a constant 3.6 V which is used as an

internal reference voltage.

Logic

The logic circuit detects the logic levels and threshold

voltages at ports LP0, LP1 and LP2 and controls the

internal functions as described in Table 2.

1997 Nov 19

8

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