ISL6141(2002) Просмотр технического описания (PDF) - Intersil
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ISL6141 Datasheet PDF : 18 Pages
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ISL6141, ISL6151
same as described above, but the active state of the output
is reversed (reference Figure 33).
If the latch is reset (GATE turns off), the internal DMOS
device (Q3) is turned off, and Q2 (NPN) turns on to clamp
the output one diode drop above the DRAIN voltage to
produce a logic low.
Once the latch is set (both DRAIN and GATE are normal), the
DMOS device (Q3) turns on and sinks current to VEE through
a 6.2KΩ resistor. The base of Q2 is clamped to VEE to turn it
off. If the external pull-up current is high enough (>1mA, for
example), the voltage drop across the resistor will be large
enough to produce a logic high output (in this example, 1mA *
6.2kΩ = 6.2V) and enable the external module.
Note that for all H versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the VDD voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
external clamp might be necessary.
OV (Over-Voltage) Pin 2 - This analog input compares the
voltage on the pin to an internal voltage reference of 1.255V
(nominal). When the input goes above the reference (low to
high transition) an Over-Voltage condition is detected and
the GATE pin is immediately pulled low to shut off the
external FET. The built in 25mV hysteresis will keep the
GATE off until the OV pin drops below 1.230V, which is the
nominal high to low threshold. A typical application will use
an external resistor divider from VDD to VEE to set the OV
level as desired. A three-resistor divider can be used to set
both OV and UV trip points.
UV (Under-Voltage) Pin 3 - This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mV. When the UV input goes below the
nominal reference (high to low transition) voltage of 1.120V,
the GATE pin is immediately pulled low to shut off the
external FET. Since the comparator has a built in 135mV
hysteresis the GATE will remain off until the UV pin rises
above a 1.255V low to high threshold. A typical application
will use an external resistor divider from VDD to VEE to set
the UV level as desired. A three-resistor divider can be used
to set both OV and UV trip points.
The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above
1.255V (nominal) to clear the latch and initiate a normal
power-up sequence.
VEE Pin 4 - This is the most negative supply voltage, such
as in a -48V system. Most of the other signals are
referenced relative to this pin, even though it may be far
away from what is considered a GND reference.
SENSE Pin 5 - This analog input monitors the voltage drop
across the external sense resistor (between SENSE and
VEE) to determine if the current exceeds the programmed
Over-Current trip point, equal to 50mV / Rsense. If the load
current exceeds the Over-Current threshold, the circuit will
regulate the current to maintain the nominal voltage drop
(50mV) across the sensing resistor R1 (Rsense). If current is
limited for more than 600µs, the Over-Current shutdown
(also called electronic circuit breaker) will quickly turn off the
FET and latch the GATE pin off.
A Hard Fault comparator is employed to detect and respond
quickly to severe short circuits. The threshold of this
comparator is set approximately four times higher (210mV)
than the Over-Current trip point. When its threshold is
exceeded the GATE is immediately (10µs typical) shut off,
the timer is reset, and a single retry (soft start) is attempted
before latching the GATE off (assuming the fault remains).
During the retry, if the fault disappears prior to the Over-
Current Time-Out period (600µs) the FET will remain on as
normal. If the GATE is latched off, the user must either
toggle the UV pin below then above its threshold, or reduce
the supply voltage below the VDD UVLO trip point and then
above it. This will clear the latch and initiate a normal power-
up sequence.
GATE Pin 6 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is
high (FET is on) when the following conditions are met:
• UVLO is above its trip point (~16.5V)
• Voltage on the UV pin is above its trip point (1.255V)
• Voltage on the OV pin is below its trip point (1.255V)
• No Over-Current conditions are present.
If any of the 4 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only when the 600µs Over-Current
Time-Out period is exceeded.
The GATE is driven high by a weak (-50µA nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA nominal pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.
DRAIN Pin 7 - This is the analog input to one of two
comparators that control the PWRGD (ISL6141) or PWRGD
(ISL6151) outputs. It compares the voltage of the external
FET DRAIN to a 1.3V internal reference (VPG). The DRAIN
voltage is criticized only until the PWRGD or PWRGD
outputs are latched into their active low or high states. The
latch is reset when any of the conditions that turn off the
GATE occur (UVLO, OV, UV, OC Time-Out). Note that the
comparator does NOT itself turn off the GATE.
VDD Pin 8 - This is the most positive power supply pin. It
can range from the Under-Voltage Lock-Out threshold
(16.5V) to +80V (Relative to VEE).
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