AD7856 Просмотр технического описания (PDF) - Analog Devices

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AD7856

5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC

Analog Devices 

AD7856

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To

attain the maximum sample rate of 285 kHz, reading and writ-

ing must be performed during conversion as in Figure 3. At

least 330 ns acquisition time must be allowed (the time from

the falling edge of BUSY to the next rising edge of CONVST)

before the next conversion begins to ensure that the part is

settled to the 14-bit level. If the user does not want to provide

the CONVST signal, the conversion can be initiated in software

by writing to the control register.

1.6mA IOL

TO OUTPUT

PIN CL

100pF

+2.1V

200␮A IOL

Figure 1. Load Circuit for Digital Output Timing

Specifications

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT = 3.5␮s MAX, 5.25␮s MAX FOR K VERSION

t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K

t1

tCONVERT

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t3

t4

THREE-STATE

1

t6

DB15

t7

t8

DB15

t9

5

6

t10

t6

DB11

t11

16

t12 THREE-

DB0

STATE

DB11

DB0

Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

t1

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT = 3.5␮s MAX, 5.25␮s MAX FOR K VERSION

t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K

tCONVERT

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t3

t4

THREE-STATE

1

t6

DB15

t7

t8

DB15

t9

5

6

t10

t6

DB11

t11

16

t12

THREE-

DB0

STATE

DB11

DB0

Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

REV. A

–5–

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