AD7856 Просмотр технического описания (PDF) - Analog Devices
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AD7856 Datasheet PDF : 32 Pages
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AD7856
TIMING SPECIFICATIONS1
(VDD = 5 V; TA = TMIN to TMAX, unless otherwise noted. A Grade: fCLKIN = 6 MHz; K Grade: fCLKIN = 4 MHz.)
␣ ␣ ␣ Limit at TMIN, TMAX
Parameter A Version
K Version Units
Description
fCLKIN2
fSCLK
t13
t2
tCONVERT
t3
t44
t54
t64
t7
t8
t9
t10
t11
t125
t13
t146
t15
t16
tCAL
tCAL1
tCAL2
500
6
6
100
50
3.5
–0.4 tSCLK
± 0.4 tSCLK
30
30
45
30
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
90
50
2.5 tCLKIN
2.5 tCLKIN
41.7
37.04
4.63
500
4
4
100
50
5.25
–0.4 tSCLK
± 0.4 tSCLK
50
50
75
40
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
90
50
2.5 tCLKIN
2.5 tCLKIN
62.5
kHz min
MHz max
MHz max
ns min
ns max
µs max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
55.5
ms typ
6.94
ms typ
Master Clock Frequency
CONVST Pulsewidth
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 20 tCLKIN
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
Delay from SYNC↓ Until DOUT 3-State Disabled
Delay from SYNC↓ Until DIN 3-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from SYNC↑ Until DOUT 3-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(250026 tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 14, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.
–4–
REV. A
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