IS61C64AH Просмотр технического описания (PDF) - Integrated Circuit Solution Inc

Номер в каталоге

Компоненты Описание

производитель

IS61C64AH

8K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Circuit Solution Inc 

IS61C64AH

AC WAVEFORMS

WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)

t WC

1

ADDRESS

VALID ADDRESS

t HA

2

OE

CE1 LOW

3

HIGH

CE2

t AW

t PWE1

4

WE

t SA

t HZWE

t LZWE

DOUT

DATA UNDEFINED

HIGH-Z

5

t SD

t HD

DIN

DATAIN VALID

6

WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)

t WC

7

ADDRESS

VALID ADDRESS

OE LOW

t HA

8

CE1 LOW

HIGH

CE2

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE2

t HZWE

HIGH-Z

t SD

t LZWE

t HD

9

10

11

DIN

DATAIN VALID

12

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the write.

2. I/O will assume the High-Z state if OE = VIH.

Integrated Circuit Solution Inc.

7

SR001-B

Share Link: