IS41C8205 Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS41C8205 Datasheet PDF : 17 Pages
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IS41C8205
IS41LV8205
ISSI ®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
VCC Speed Min. Max. Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
–5
5 µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
–5
5 µA
VOH
Output High Voltage Level
IOH = –5.0 mA, Vcc = 5V
IOH = –2.0 mA, Vcc = 3.3V
2.4 — V
VOL
Output Low Voltage Level
IOL = 4.2 mA, Vcc = 5V
IOL = 2 mA, Vcc = 3.3V
ICC1
Standby Current: TTL
RAS, CAS ≥ VIH Commercial
Industrial
5V
3.3V
5V
3.3V
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
5V
3.3V
— 0.4 V
2 mA
— 0.5
—
3
—
2
—
1 mA
— 0.5
ICC3
Operating Current:
RAS, CAS,
Random Read/Write(2,3)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4
Operating Current:
RAS= VIL, CAS ≥ VIH
Fast Page Mode(2,3,4)
tRC = tRC (min.)
Average Power Supply Current
-50
— 120 mA
-60
— 110
-50
—
90 mA
-60
—
80
ICC5
Refresh Current:
RAS-Only(2,3)
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
Average Power Supply Current
-50
— 120 mA
-60
— 110
ICC6
Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50
— 120 mA
-60
— 110
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
06/24/01
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