IS25LQ016 Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS25LQ016 Datasheet PDF : 52 Pages
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16 Mbit Single Operating Voltage Serial Flash Memory With 104
MHz Dual- or 100MHz Quad-Output SPI Bus Interface
REGISTERS (CONTINUED)
IS25LQ016
Table 6. Status Register Bit Definition
Bit Name
Definition
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
WIP
WEL
BP0
BP1
BP2
BP3
QE
SRWD
Write In Progress Bit:
"0" indicates the device is ready
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Tables 7, 8 and 9 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 10 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read-
/Write
R
R/W
R/W
R/W
R/W
Non-Volatile
bit
No
No
Yes
Yes
Yes
Table 9. Block Write Protect Bits for IS25LQ016C
Status Register Bits
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Memory Area
16 Mbit
None
(1 blocks : 31th):
(2 blocks :30th to 31th):
(4 blocks :28th to31th):
(8 blocks :24th to 31th):
(16 blocks :16th to 31th):
All blocks (32 blocks : 0 to 31):
(16 blocks :0th to 15th):
(24 blocks :0th to 23th):
(28 blocks :0th to 27th):
(30 blocks :0th to 29th):
(31 blocks :0th to 30th):
All blocks (32 blocks : 0th to 31th):
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/20/2012
9
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