IS24C64 Просмотр технического описания (PDF) - Integrated Silicon Solution

Номер в каталоге

Компоненты Описание

производитель

IS24C64

65,536-bit/32,768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C32-2/3

IS24C64-2/3

ISSI ®

DEVICE OPERATION

The IS24CXX family features a serial communication and

supports a bi-directional 2-wire bus transmission protocol.

2-WIRE BUS

The two-wire bus is defined as a Serial Data line (SDA), and a Serial

ClockLine(SCL). Theprotocoldefinesanydevicethatsendsdata

onto the SDA bus as a transmitter, and the receiving devices as a

receiver. ThebusiscontrolledbyMASTERdevicewhichgenerates

the SCL, controls the bus access and generates the STOP and

STARTconditions. TheIS24CXXistheSLAVEdeviceonthebus.

The Bus Protocol:

– Data transfer may be initiated only when the bus is not busy

– During a data transfer, the data line must remain stable

whenever the clock line is high. Any changes in the

data line while the clock line is high will be interpreted

as a START or STOP condition.

The state of the data line represents valid data when after

a START condition, the data line is stable for the duration

of the HIGH period of the clock signal. The data on the

SDA line may be changed during the LOW period of the

clock signal. There is one clock pulse per bit of data. Each

data transfer is initiated with a START condition and

terminated with a STOP condition.

START Condition

The START condition precedes all commands to the device

and is defined as a HIGH to LOW transition of SDA when

SCL is HIGH. The IS24CXX monitors the SDA and SCL

lines and will not respond until the START condition is met.

STOP Condition

The STOP condition is defined as a LOW to HIGH

transition of SDA when SCL is HIGH. All operations must

end with a STOP condition.

ACKnowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line.

DEVICE ADDRESSING

The MASTER begins a transmission by sending a START

condition. TheMASTERthensendstheaddressoftheparticular

slave devices it is requesting. The SLAVE (Fig. 5) address is 8 bits.

The four most significant bits of the address are fixed as

1010 for the IS24CXX.

The 32K/64K uses the three device address bits A2, A1,

A0 to allow as many as eight devices on the same bus.

These bits must compare to their corresponding hardwired

input pins. The A2, A1, and A0 pins use an internal

proprietary circuit that biases them to a logic low condition

if the pins are allowed to float.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set

to 1, a Read operation is selected, and when set to 0, a

Write operation is selected.

After the MASTER sends a START condition and the

SLAVE address byte, the IS24CXX monitors the bus and

responds with an Acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

IS24CXX pulls down the SDA line during the ninth clock

cycle, signaling that it received the eight bits of data. The

IS24CXX then performs a Read or Write operation

depending on the state of the R/W bit.

WRITE OPERATION

Byte Write

In the Byte Write mode, the Master device sends the START

condition and the slave address information (with the R/W

set to Zero) to the Slave device. After the Slave generates

an acknowledge, the Master sends two byte addresses that

are to be written into the address pointer of the

IS24CXX. After receiving another acknowledge from the

Slave, the Master device transmits the data byte to be written

intotheaddressmemorylocation. TheIS24CXXacknowledges

once more and the Master generates the STOP condition,

at which time the device begins its internal programming

cycle. While this internal cycle is in progress, the device

will not respond to any request from the Master device.

Page Write

The IS24CXX is capable of 32-byte page-WRITE operation.

A page-WRITE is initiated in the same manner as a byte

write, but instead of terminating the internal write cycle after

the first data word is transferred, the master device can

transmit up to 31 more bytes. After the receipt of each data

word, the IS24CXX responds immediately with an

ACKnowledge on SDA line, and the five lower order data

word address bits are internally incremented by one, while

the five higher order bits of the data word address remain

constant. If the master device should transmit more than

32 words, prior to issuing the STOP condition, the address

counter will “roll over,” and the previously written data will

be overwritten. Once all 32 bytes are received and the

STOP condition has been sent by the Master, the internal

programming cycle begins. At this point, all received data

is written to the IS24CXX in a single write cycle. All inputs

are disabled until completion of the internal WRITE cycle.

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

PRELIMINARY INFORMATION Rev. 00B

04/04/01

Share Link: