IS24C64 Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS24C64

65,536-bit/32,768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C32-2/3

IS24C64-2/3

FUNCTIONAL BLOCK DIAGRAM

ISSI ®

Vcc 8

SDA 5

SCL 6

WP 7

SLAVE ADDRESS

REGISTER &

COMPARATOR

CONTROL

LOGIC

WORD ADDRESS

COUNTER

GND 4

ACK

nMOS

HIGH VOLTAGE

GENERATOR,

TIMING & CONTROL

EEPROM

ARRAY

Y

DECODER

Clock

DI/O

> DATA

REGISTER

PIN DESCRIPTIONS

A0-A2

SDA

SCL

WP

Vcc

GND

Address Inputs

Serial Address/Data I/O

Serial Clock Input

Write Protect Input

Power Supply

Ground

SCL

This input clock pin is used to synchronize the data

transfer to and from the device.

SDA

The SDA is a Bi-directional pin used to transfer addresses

and data into and out of the device. The SDA pin is an open

drain output and can be wire-Ored with other open drain

or open collector outputs. The SDA bus requires a pullup

resistor to Vcc.

A0, A1, A2

The A0, A1 and A2 are the device address inputs that are

hardwired or left not connected for hardware compatibility

PIN CONFIGURATION

8-Pin DIP and SOIC

A0 1

A1 2

A2 3

GND 4

8 VCC

7 WP

6 SCL

5 SDA

with the 24C16. When pins are hardwired, as many as

eight 32K/64K devices may be addressed on a single bus

system. When the pins are not hardwired, the default A0,

A1,and A2 are zero..

WP

WP is the Write Protect pin. If the WP pin is tied to Vcc

the entire array becomes Write Protected (Read only).

When WP is tied to GND or left floating normal read/write

operations are allowed to the device.

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

04/04/01

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