IS24C16-2 Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS24C16-2 Datasheet PDF : 11 Pages
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IS24C16-2, IS24C16-3
IS24C08-2, IS24C08-3
ISSI ®
counter will “roll over,” and the previously written data will
be overwritten. Once all 16 bytes are received and the
STOP condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data
is written to the IS24CXX in a single write cycle. All inputs
are disabled until completion of the internal WRITE cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation, the
IS24CXX initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address for a write operation.
If the IS24CXX is still busy with the write operation, no ACK
will be returned. If the IS24CXX has completed the write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
slave address is set to “1”. There are three READ operation
options: current address read, random address read and
sequential read.
Current Address Read
The IS24CXX contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a read or write operation addressed to the address
location n, the internal address counter would increment to
address location n+1. When the IS24CXX receives the
Device Addressing Byte with a READ operation (read/write
bit set to “1”), it will respond an ACKnowledge and transmit
the 8-bit data word stored at address location n+1. The
master will not acknowledge the transfer but does generate
a STOP condition and the IS24CXX discontinues
transmission. If 'n' is the last byte of the memory, then the
data from location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
Random Access Read
Selective READ operations allow the Master device to
select at random any memory location for a READ operation.
The Master device first performs a 'dummy' write operation
by sending the START condition, slave address and word
address of the location it wishes to read. After the IS24CXX
acknowledge the word address, the Master device resends
the START condition and the slave address, this time with
the R/W bit set to one. The IS24CXX then responds with
its acknowledge and sends the data requested. The master
device does not send an acknowledge but will generate a
STOP condition. (Refer to Figure 9. Random Address
Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24CXX sends initial byte sequence, the master device
now responds with an ACKnowledge indicating it requires
additional data from the IS24CXX. The IS24CXX continues
to output data for each ACKnowledge received. The master
device terminates the sequential READ operation by pulling
SDA HIGH (no ACKnowledge) indicating the last data
word to be read, followed by a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n+1, ... etc.
The address counter increments by one automatically,
allowing the entire memory contents to be serially read
during sequential read operation. When the memory
address boundary (2047 for IS24C16-2 and IS24C16-3;
1023 for IS24C08-2 and IS24C08-3) is reached, the address
counter “rolls over” to address 0, and the IS24CXX-2
continues to output data for each ACKnowledge received.
(Refer to Figure 10. Sequential Read Operation Starting
with a Random Address READ Diagram.)
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/29/00
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