MT4LC4M16F5-6 Просмотр технического описания (PDF) - Micron Technology
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MT4LC4M16F5-6 Datasheet PDF : 19 Pages
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DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
DRAM array at least once every 64ms. The recom-
mended procedure is to execute 4,096 CBR REFRESH
cycles, either uniformly spaced or grouped in bursts,
every 64ms. The MT4LC4M16F5 internally refreshes
one row for every CBR cycle, so executing 4,096 CBR
cycles covers all rows. The CBR REFRESH will invoke the
internal refresh counter for automatic RAS# address-
4 MEG x 16
FPM DRAM
ing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method some
compatibility issues may become apparent. JEDEC
strongly recommends the use of CBR REFRESH for this
device.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
RAS#
WORD WRITE
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
0
X
1
1
1
1
X
0
0
0
UPPER BYTE
0
X
1
1
1
(DQ8-DQ15)
1
X
0
0
0
OF WORD
0
X
1
1
1
0
X
1
1
1
0
X
1
1
1
0
X
1
1
1
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
X
1
X
0
X
1
X
0
X
1
X
1
X
1
X
1
ADDRESS 1
Figure 1
WORD and BYTE WRITE Example
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
3
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©2000, Micron Technology, Inc.
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