LH28F400SUB-Z0 Просмотр технического описания (PDF) - Sharp Electronics
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LH28F400SUB-Z0 Datasheet PDF : 34 Pages
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4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
LH28F008SA-Compatible Mode Command Bus Definitions
COMMAND
Read Array
Intelligent Identifier
Read Compatible Status Register
Clear Status Register
Word Write
Alternate Word Write
Block Erase/Confirm
Erase Suspend/Resume
FIRST BUS CYCLE
OPER. ADDRESS DATA
Write
X
FFH
Write
X
90H
Write
X
70H
Write
X
50H
Write
X
40H
Write
X
10H
Write
X
20H
Write
X
B0H
SECOND BUS CYCLE
OPER. ADDRESS DATA
Read
AA
AD
Read
IA
ID
Read
X
CSRD
Write
WA
WD
Write
WA
WD
Write
BA
D0H
Write
X
D0H
NOTE
1
2
3
4
4
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed.
LH28F400SU Performance Enhancement Command Bus Definitions
COMMAND
Protect Set/Confirm
Protect Reset/Confirm
Lock Block/Confirm
Erase All Unlocked
Blocks
Two-Byte Write
FIRST BUS CYCLE SECOND BUS CYCLE
MODE
OPER. ADD. DATA OPER. ADD. DATA
Write X 57H Write 0FFH D0H
Write X 47H Write 0FFH D0H
Write X 77H Write BA D0H
THIRD BUS CYCLE
OPER. ADD. DATA
NOTE
1, 2
3
1, 2, 4
Write X A7H Write X
D0H
1, 2
x8 Write X FBH Write A1 WD (L, H) Write WA WD (H, L) 1, 2, 5
ADDRESS
BA = Block Address
WA = Write Address
X = Don’t Care
DATA
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
NOTES:
1. After initial device power-up, or return from deep power-down mode, the block lock status bits default to the locked state independent of
the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A-1 is automatically complemented to load second byte of data A-1 value determines which WD is supplied first: A-1 = 0 looks at the
WDL, A-1 = 1 looks at the WDH. In word-wide (x16) mode A-1 don't care.
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1,
others are don’t care.
7
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