LH28F400SUB-Z0 Просмотр технического описания (PDF) - Sharp Electronics
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LH28F400SUB-Z0 Datasheet PDF : 34 Pages
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LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
START
WRITE 20H
WRITE D0H AND
BLOCK ADDRESS
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
0
CSR.7 =
SUSPEND YES
ERASE
1
CSR FULL STATUS
CHECK IF DESIRED
BUS
OPERATION
COMMAND
COMMENTS
Write
Block Erase D = 20H
A=X
Write
Confirm
D = D0H
A = BA
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
0
CSR.4, 5 =
1
ERASE
SUCCESSFUL
1
CSR.3 =
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
VPP LOW
DETECT
BUS
OPERATION
COMMAND
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command.
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Single Block Erase command.
If power is off or RP is set low during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
Figure 5. Block Erase with Compatible Status Register
28F400SUB-5
10
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