X24C04S8I-3 Просмотр технического описания (PDF) - Xicor -> Intersil
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X24C04S8I-3 Datasheet PDF : 18 Pages
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X24C04
Current Address Read
Internally the X24C04 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
a read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of
the slave address with the R/W bit set to one, the
X24C04 issues an acknowledge and transmits the eight
bit word. The read operation is terminated by the master;
by not responding with an acknowledge and by issuing
a stop condition. Refer to Figure 7 for the sequence of
address, acknowledge and data transfer.
Figure 7. Current Address Read
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to
issuing the slave address with the R/W bit set to one,
the master must first perform a “dummy” write opera-
tion. The master issues the start condition, and the
slave address followed by the word address it is to read.
After the word address acknowledge, the master im-
mediately reissues the start condition and the slave
address with the R/W bit set to one. This will be followed
by an acknowledge from the X24C04 and then by the
eight bit word. The read operation is terminated by the
master; by not responding with an acknowledge and by
issuing a stop condition. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.
S
T
BUS ACTIVITY: A
MASTER
R
T
SLAVE
ADDRESS
S
DATA
T
O
P
SDA LINE
S
P
A
BUS ACTIVITY:
C
X24C04
K
3839 FHD F13
Figure 8. Random Read
S
T
BUS ACTIVITY: A
MASTER
R
T
SLAVE
ADDRESS
WORD
ADDRESS n
S
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
S
A
A
A
BUS ACTIVITY:
C
C
C
X24C04
K
K
K
DATA n
S
T
O
P
P
3839 FHD F14
7
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