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IR2161SPBF

HALOGEN CONVERTOR CONTROL IC

International Rectifier 

IR2161(S) & (PbF)

across the CSD capacitor will vary from 0V if there is no

load to approximately 5V at maximum load.

This is provided that the correct value of current sense

resistor has been selected for the maximum rated load and

line voltage supply of the convertor. This should be 0.33

Ohm (0.5W) for a 100W system running from a 220-240V

AC line. (It should be noted that the RCS resistor value is

also critical for setting the limits for the shut down circuit)

In RUN mode the oscillator frequency will vary from

approximately 34kHz when VCSD is 5V (maximum load) to

70kHz when VCSD is 0V (no load). The result of this is that

if a lighter load, such as a single 35W lamp, is connected to

a 100W convertor, the frequency will shift upwards so that

the output voltage falls below the maximum that is desirable

for the lamp. This provides sufficient compensation for the

load to ensure that the lamp voltage will always be within

acceptable limits but does not require a complicated regulation

scheme involving feedback from the output.

An additional internal current source has been included to

discharge the external capacitor. This will provide

approximately 10% ripple at twice the line frequency if CSD

is 100nF.

The advantage of this is that during the line voltage half

cycle the oscillator frequency will vary by several kHz thus

spreading the EMI conducted and radiated emissions over

a range of frequencies and avoiding high amplitude peaks

at particular frequencies. In this way the filter components

used may be similar to those used in a common bipolar self-

Figure 6, VS voltage and CSD voltage.

In the above trace it can be seen that a leading edge phase

cut (triac) dimmer is connected at close to maximum

brightness. There is a short delay at the beginning of each

half cycle before the AC line voltage is switched to the

convertor. Dimming increases the ripple in the CSD voltage

and gives more modulation. This is an inherent effect that

causes no system problems.

The startup sequence of the CSD pin can be seen from the

point where VCC increases above the UVLO+ threshold.

AV > 13

CS

CSD

150K

12K

oscillating system.

Figure 5, Voltage Compensation Circuit

10

Figure 7, Startup sequence of CSD.

This trace shows that after the CSD voltage has ramped up

through soft start, the system switches over to voltage com-

pensation mode and a ripple exists which allows the fre-

quency modulation (or “dither”) to occur. In this case the

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