M66242P Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M66242P

4-CH 12-BIT PWM GENERATOR

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66242P/FP

4-CH 12-BIT PWM GENERATOR

The “H” width of undesignated subsections remains un-

changed.

As explained above, one cycle of waveform is a combina-

tion of two waveforms different in the “H” width.

(In Fig. 2 above, one cycle consists of 10 subsections

whose H width is 74 × τ and 6 subsections whose “H”

width is 75 × τ.)

Note: It is impossible to set one whole cycle to “H” level.

(2) 8-bit PWM output

As can be seen from the 12-bit PWM waveform output

process as described above, 8-bit resolution PWM wave-

form can be output by fixing the lower 4 bits of PWM data

to 00002.

All subsections from t10 to t15 have the “H” width as deter-

mined by the upper 8 bits of PWM data.

Note: It is impossible to set one whole cycle to “H” level.

Output Control

(1) Serial data input

By using data on lower byte register b3 (output control se-

lection bit), output of each channel can be controlled inde-

pendently. The state of the selected PWM output changes

after the completion of the ongoing cycle.

When b3 is set 0, lower byte register b0 (write data desig-

nation bit) is reset. Do not write on upper byte in this case.

(2) Output control input

The status of all 4 channel outputs during a cycle is deter-

mined depending on the status of output control input OC

at the start of the cycle. (See Fig. 6.)

Even when output is in a high-impedance state, data on

each PWM register is retained, and data can be rewritten.

(3) Reset

When reset input R turns “L”, all operation is reset as soon

as the ongoing cycle is completed: The outputs of all 4

channels turns high-impedance. The PWM register of

each channel is reset.

When R is shifted from “L” to “H”, a next cycle starts, and

data writing becomes possible. However, outputs stay in

the high-impedance state. (See Fig. 6.)

To resume output, write input data for each channel.

Initial State

After power-on, outputs and PWM register data are unstable.

(1) Reset

Reset input R is kept on “L” level for more than one cycle

(2.048ms when fXIN is 4 MHz) or more, this integrated cir-

cuit is put in a reset state.

If stabilization needs more time, e. g. when a quartz reso-

nator is used, keep R on “L” level for an adequate period of

time.

(2) Serial data input

When starting using this integrated circuit without reset-

ting, input false lower byte data (b0 =0) to stabilize lower

byte register b0 data, and then input normal data.

WR

SIN

SCLK

PWM output

Fig. 3 Serial Data Write Timing

b0 b1 b2 b3 b4 b5 b6 b7

Ongoing cycle

Next cycle

5

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