INTEL386 Просмотр технического описания (PDF) - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

Segment Registers Six 16-bit special purpose reg-

isters select at any given time the segments of

memory that are immediately addressable for code

stack and data

Flags and Instruction Pointer Registers The two

32-bit special purpose registers in figure 2 1 record

or control certain aspects of the Intel386 SX Micro-

processor state The EFLAGS register includes

status and control bits that are used to reflect the

outcome of many instructions and modify the se-

mantics of some instructions The Instruction Point-

er called EIP is 32 bits wide The Instruction Pointer

controls instruction fetching and the processor auto-

matically increments it after executing an instruction

Control Registers The four 32-bit control register

are used to control the global nature of the Intel386

SX Microprocessor The CR0 register contains bits

that set the different processor modes (Protected

Real Paging and Coprocessor Emulation) CR2 and

CR3 registers are used in the paging operation

System Address Registers These four special

registers reference the tables or segments support-

ed by the 80286 Intel386 SX Intel386 DX CPU’s

protection model These tables or segments are

GDTR (Global Descriptor Table Register)

IDTR (Interrupt Descriptor Table Register)

LDTR (Local Descriptor Table Register)

TR (Task State Segment Register)

Debug Registers The six programmer accessible

debug registers provide on-chip support for debug-

ging The use of the debug registers is described in

Section 2 10 Debugging Support

Test Registers Two registers are used to control

the testing of the RAM CAM (Content Addressable

Memories) in the Translation Lookaside Buffer por-

tion of the Intel386 SX Microprocessor Their use is

discussed in Testability

Figure 2 2 Status and Control Register Bit Functions

240187 – 3

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