IP1000ALF-DS-R01 Просмотр технического описания (PDF) - Unspecified

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IP1000ALF-DS-R01

Gigabit Ethernet NIC Single Chip

Unspecified 

PIN Description (continued)

IP1000A LF

Preliminary Data Sheet

Pin no.

Label

Main Clock

31

X2

32

X1

PCI interface

60

VDET

59

INTAN

61

RSTN

63

PMEN

108

PAR

100

FRAMEN

102

TRDYN

Type

Description

O Reference Clock.

25 MHz crystal reference.

I Reference Clock.

25 MHz crystal reference or oscillator input.

I Power Detect.

The IP1000A LF detects whether PCI bus power supply is

available or not from this pin.

O Interrupt Request, asserted LOW.

The IP1000A LF asserts INTAN to request an interrupt,

when any one of the programmed interrupt event occurs.

I Reset, asserted LOW.

RSTN will cause the IP1000A LF to reset all of its functional

blocks. RSTN must be asserted for a minimum duration of

10 PCICLK cycles. While RSTN is asserted, the IP1000A

LF PCI interface is placed in an isolated state. When the

IP1000A LF PCI bus is isolated, all PCI output and

bi-directional signals are placed in a high impedance state,

and all inputs are ignored. The IP1000A LF will remain in a

reset state for approximately 380ns following the

de-assertion of RSTN.

O Wake Event, assertion level is programmable. The

IP1000A LF asserts PMEN to signal the detection of a wake

event. The PMEN signal eventually drives the PCI bus

PME# signal, but not intended to be directly connected to

PME#. See the PCI Bus Power Management Interface

Specification for details on generating PME# from PMEN.

I/O Parity.

PCI Bus parity is even across bits 0 through 31 of AD and

bits 0 through 3 of CBEN. The IP1000A LF generates PAR

during address and write data phases as a bus master, and

during read data phase as a target. It checks for correct

parity during read data phase as bus master, during every

address phase as a bus slave, and during write data phases

as a target.

I/O PCI Bus Cycle Frame, asserted LOW.

FRAMEN is asserted at the beginning of the address phase

of the bus transaction and de-asserted before the final

transfer of the data phase of the transaction.

I/O Target Ready, asserted LOW.

A bus target asserts TRDYN to indicate valid read data

phases, and to indicate it is ready to accept data during

write data phases. A bus master will monitor TRDYN.

7/75

Copyright © 2005, IC Plus Corp.

July 5, 2005

IP1000A LF-DS-R08

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