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IP100A

Integrated 10/100 Ethernet MAC + PHY

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3 PIN Descriptions

IP100A LF

Preliminary Data Sheet

PIN NAME PIN TYPE

PIN DESCRIPTION

PCI INTERFACE

RSTN

INPUT

Reset, asserted LOW. RSTN will cause the IP100A LF to reset all of its

functional blocks. RSTN must be asserted for a minimum duration of 10

PCICLK cycles.

PCICLK

INPUT

PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the

internal DMA logic. All bus signals are sampled on the rising edges of

PCICLK. PCICLK can operate from 25MHz to 33MHz.

GNTN

INPUT

PCI Bus Grant, asserted LOW. GNTN signals access to the PCI bus has

been granted to IP100A LF.

IDSEL

INPUT

Initialization Device Select. The IDSEL is used to select the IP100A LF

during configuration read and write transactions.

INTAN

OUTPUT

Interrupt Request, asserted LOW. The IP100A LF asserts INTAN to

request an interrupt, when any one of the programmed interrupt event

occurs.

PMEN

OUTPUT

Wake Event, assertion level is programmable (see the WakePolarity bit of

the WakeEvent register). The IP100A LF asserts PMEN to signal the

detection of a wake event.

REQN

OUTPUT Request, asserted LOW. The IP100A LF asserts REQN to request PCI bus

master operation.

AD

[31..0]

IN/OUT

PCI Bus Address/Data. Address and data are multiplexed on the AD pins.

The AD pins carry the physical address during the first clock cycle of a

transaction, and carry data during the subsequent clock cycles.

CBEN

[3..0]

IN/OUT

PCI Bus Command/Byte Enable, asserted LOW. Bus command and byte

enables are multiplexed on the CBEN pins. CBEN specify the bus

command during the address phase transaction, and carry byte enables

during the data phase.

PAR

IN/OUT

Parity. PCI Bus parity is even across AD[31..0] and CBEN[3..0]. The

IP100A LF generates PAR during address and write data phases as a bus

master, and during read data phase as a target. It checks for correct PAR

during read data phase as bus master, during every address phase as a

bus slave, and during write data phases as a target.

FRAMEN

IN/OUT

PCI Bus Cycle Frame, asserted LOW. FRAMEN is an indication of a

transaction. It is asserted at the beginning of the address phase of the bus

transaction and de-asserted before the final transfer of the data phase of

the transaction.

IRDYN

IN/OUT

Initiator Ready, asserted LOW. A bus master asserts IRDYN to indicate

valid data phases on AD[31..0] during write data phases, indicates it is

ready to accept data during read data phases. A target will monitor IRDYN.

TRDYN

IN/OUT

Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid

read data phases, and to indicate it is ready to accept data during write

data phases. A bus master will monitor TRDYN.

STOPN

IN/OUT

Stop, asserted LOW. STOPN is driven by the slave target to inform the bus

master to terminate the current transaction.

TABLE 2 : IP100A LF Pin Descriptions

9/97

Copyright © 2004, IC Plus Corp.

March. 30, 2007

IP100A LF-DS-R17

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