IL41050TE(2010) Просмотр технического описания (PDF) - Unspecified
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IL41050TE Datasheet PDF : 10 Pages
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IL41050
Absolute Maximum Ratings(1) (2)
Parameters
Storage temperature
Ambient operating temperature
DC voltage at CANH and CANL pins
Supply voltage
Digital input voltage
Digital output voltage
DC voltage at VREF
Transient Voltage at CANH or CANL
Electrostatic discharge at all pins
Electrostatic discharge at all pins
Symbol
TS
TA
VCANH VCANL
VDD1 , VDD2
VTxD , VS
VRxD
VREF
Vtrt(CAN)
Vesd
Vesd
Min.
−55
−55
−27
−0.5
−0.3
−0.3
−0.3
−200
−4,000
−200
Typ.
Max.
150
135
40
6
VDD + 0.3
VDD + 0.3
VDD + 0.3
200
4,000
200
Units
°C
°C
V
V
V
V
V
V
V
V
Test Conditions
0 V< VDD2 < 5.25 V;
indefinite duration
Human body model
Machine model
Recommended Operating Conditions
Parameters
Symbol
Supply voltage
Input voltage at any bus terminal
(separately or common mode)
VDD1
VDD2
VCANH
VCANL
High-level digital input voltage (3) (4)
VIH
Low-level digital input voltage (3) (4)
Digital output current (RxD)
Ambient operating temperature
Digital input signal rise and fall times
VIL
IOH
TA
tIR, tIF
Insulation Specifications
Parameters
Creepage distance (external)
Barrier impedance
Leakage current
Symbol
Min.
3.0
4.75
−12
2.0
2.4
2.0
0
−8
−55
Typ.
Max.
5.5
5.25
12
VDD1
VDD1
VDD2
0.8
8
125
1
Min.
8.08
Typ.
> 1014 || 7
0.2
Max.
Safety and Approvals
IEC61010-2001
TUV Certificate Numbers:
N1502812 (pending)
Classification: Reinforced Insulation
Model
Package
IL41050
SOIC (0.15" and 0.3")
Pollution Degree
II
Material Group
III
UL 1577
Component Recognition Program File Number: E207481 (pending)
Rated 2,500VRMS for 1 minute
Units
V
V
V
V
mA
°C
μs
Test Conditions
VDD1 = 3.3 V
VDD1 = 5.0 V
VDD2 = 5.0 V
VDD1 = 3.3V to 5V
Units
mm
Ω || pF
μARMS
Test Conditions
240 VRMS, 60 Hz
Max. Working Voltage
300 VRMS
Soldering Profile
Per JEDEC J-STD-020C
Moisture Sensitivity Level: MSL=2
Notes:
1. Absolute Maximum specifications mean the device will not be damaged if operated under these conditions. It does not guarantee performance.
2. All voltages are with respect to network ground except differential I/O bus voltages.
3. The TxD input is edge sensitive. Voltage magnitude of the input signal is specified, but edge rate specifications must also be met.
4. The maximum time allowed for a logic transition at the TxD input is 1 μs.
2
NVE Corporation 11409 Valley View Road, Eden Prairie, MN 55344-3617 Phone: (952) 829-9217 Fax: (952) 829-9189 www.IsoLoop.com ©NVE Corporation
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