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IDT82V3380A

SYNCHRONOUS ETHERNET IDT WAN PLL™

Integrated Device Technology 

IDT82V3380A

SYNCHRONOUS ETHERNET WAN PLL™

8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 152

8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 152

8.4 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 153

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 154

9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 154

9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 154

9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 155

9.3.1 AMI Input / Output Port ................................................................................................................................................................ 155

9.3.1.1 Structure ......................................................................................................................................................................... 155

9.3.1.2 I/O Level ......................................................................................................................................................................... 155

9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 157

9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 157

9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 158

9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 158

9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 160

9.3.3.3 Single-Ended Input for Differential Input ........................................................................................................................ 161

9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 162

9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 165

9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 166

9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 167

PACKAGE DIMENSIONS.................................................................................................................................................... 173

ORDERING INFORMATION................................................................................................................................................ 176

............................................................................................................................................................................................. 177

Table of Contents

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May 16, 2011

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