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IDT82V3380A

SYNCHRONOUS ETHERNET IDT WAN PLL™

Integrated Device Technology 

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19

3.1 RESET ........................................................................................................................................................................................................... 19

3.2 MASTER CLOCK .......................................................................................................................................................................................... 19

3.3 INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20

3.3.1 Input Clocks .................................................................................................................................................................................... 20

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23

3.5.1 LOS Monitoring .............................................................................................................................................................................. 23

3.5.2 Activity Monitoring ......................................................................................................................................................................... 23

3.5.3 Frequency Monitoring ................................................................................................................................................................... 24

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25

3.6.2 Forced Selection ............................................................................................................................................................................ 26

3.6.3 Automatic Selection ....................................................................................................................................................................... 26

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27

3.7.1.1 Fast Loss .......................................................................................................................................................................... 27

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27

3.7.2 Locking Status ............................................................................................................................................................................... 27

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29

3.8.1 Input Clock Validity ........................................................................................................................................................................ 29

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29

3.8.2.1 Revertive Switch ............................................................................................................................................................... 29

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34

3.10.1.3 Locked Mode .................................................................................................................................................................... 34

Table of Contents

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May 16, 2011

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