IDT82P2288 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82P2288 Datasheet PDF : 384 Pages
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.27.2.6 Analog Loopback .............................................................................................................................................................. 92
3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................... 92
3.28 INTERRUPT SUMMARY .............................................................................................................................................................................. 95
4 OPERATION .................................................................................................................................................................... 96
4.1 POWER-ON SEQUENCE ............................................................................................................................................................................. 96
4.2 RESET .......................................................................................................................................................................................................... 96
4.3 RECEIVE / TRANSMIT PATH POWER DOWN ........................................................................................................................................... 96
4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................. 97
4.4.1 SPI Mode ......................................................................................................................................................................................... 97
4.4.2 Parallel Microprocessor Interface ................................................................................................................................................ 98
4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................. 99
4.5.1 Indirect Register Read Access ..................................................................................................................................................... 99
4.5.2 Indirect Register Write Access ..................................................................................................................................................... 99
5 PROGRAMMING INFORMATION ................................................................................................................................. 100
5.1 REGISTER MAP ......................................................................................................................................................................................... 100
5.1.1 T1/J1 Mode .................................................................................................................................................................................... 100
5.1.1.1 Direct Register ................................................................................................................................................................ 100
5.1.1.2 Indirect Register ............................................................................................................................................................. 105
5.1.2 E1 Mode ........................................................................................................................................................................................ 106
5.1.2.1 Direct Register ................................................................................................................................................................ 106
5.1.2.2 Indirect Register ............................................................................................................................................................. 111
5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 113
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 114
5.2.1.1 Direct Register ................................................................................................................................................................ 114
5.2.1.2 Indirect Register ............................................................................................................................................................. 216
5.2.2 E1 Mode ........................................................................................................................................................................................ 229
5.2.2.1 Direct Register ................................................................................................................................................................ 229
5.2.2.2 Indirect Register ............................................................................................................................................................. 332
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 347
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) .................................................................................................................. 348
6.2 JTAG DATA REGISTER ............................................................................................................................................................................ 349
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 349
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 349
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 349
6.3 TEST ACCESS PORT CONTROLLER ...................................................................................................................................................... 352
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 355
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 355
7.2 RECOMMENDED OPERATING CONDITIONS ......................................................................................................................................... 355
7.3 D.C. CHARACTERISTICS ......................................................................................................................................................................... 356
7.4 DIGITAL I/O TIMING CHARACTERISTICS ............................................................................................................................................... 357
7.5 CLOCK FREQUENCY REQUIREMENT .................................................................................................................................................... 357
7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................... 358
7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................................................ 359
7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................ 360
7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................ 361
7.10 JITTER TOLERANCE ................................................................................................................................................................................ 362
7.10.1 T1/J1 Mode .................................................................................................................................................................................... 362
7.10.2 E1 Mode ........................................................................................................................................................................................ 363
7.11 JITTER TRANSFER ................................................................................................................................................................................... 364
7.11.1 T1/J1 Mode .................................................................................................................................................................................... 364
7.11.2 E1 Mode ........................................................................................................................................................................................ 365
7.12 MICROPROCESSOR TIMING SPECIFICATION ....................................................................................................................................... 366
7.12.1 Motorola Non-Multiplexed Mode ................................................................................................................................................. 366
Table of Contents
iv
March 22, 2004
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