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IDT82P2288

Octal T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

List of Figures

Figure 1. 256-Pin PBGA (Top View) ............................................................................................................................................................................. 3

Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 15

Figure 3. Monitoring Receive Path .............................................................................................................................................................................. 16

Figure 4. Monitoring Transmit Path ............................................................................................................................................................................. 16

Figure 5. Jitter Attenuator ............................................................................................................................................................................................ 18

Figure 6. AMI Bipolar Violation Error ........................................................................................................................................................................... 20

Figure 7. B8ZS Excessive Zero Error ......................................................................................................................................................................... 20

Figure 8. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................. 20

Figure 9. E1 Frame Searching Process ...................................................................................................................................................................... 31

Figure 10. Basic Frame Searching Process ................................................................................................................................................................ 32

Figure 11. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 34

Figure 12. Standard HDLC Packet .............................................................................................................................................................................. 45

Figure 13. Overhead Indication In The FIFO ............................................................................................................................................................... 46

Figure 14. Standard SS7 Packet ................................................................................................................................................................................. 47

Figure 15. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 51

Figure 16. Signaling Output In E1 Mode ...................................................................................................................................................................... 51

Figure 17. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 56

Figure 18. T1/J1 To E1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 56

Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 57

Figure 20. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 58

Figure 21. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 58

Figure 22. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 59

Figure 23. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 59

Figure 24. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 63

Figure 25. E1 To T1/J1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 63

Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 64

Figure 27. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 65

Figure 28. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 65

Figure 29. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 66

Figure 30. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 66

Figure 31. DSX-1 Waveform Template ........................................................................................................................................................................ 81

Figure 32. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 81

Figure 33. E1 Waveform Template .............................................................................................................................................................................. 81

Figure 34. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 81

Figure 35. G.772 Non-Intrusive Monitor ...................................................................................................................................................................... 93

Figure 36. Hardware Reset When Powered-Up .......................................................................................................................................................... 96

Figure 37. Hardware Reset In Normal Operation ........................................................................................................................................................ 96

Figure 38. Read Operation In SPI Mode ..................................................................................................................................................................... 97

Figure 39. Write Operation In SPI Mode ...................................................................................................................................................................... 97

Figure 40. JTAG Architecture .................................................................................................................................................................................... 347

Figure 41. JTAG State Diagram ................................................................................................................................................................................ 354

Figure 42. I/O Timing in Mode ................................................................................................................................................................................... 357

Figure 43. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 362

Figure 44. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 363

Figure 45. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 364

Figure 46. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 365

Figure 47. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 366

Figure 48. Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... 367

List of Figures

viii

March 22, 2004

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