IDT82P2288(2009) Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
производитель
IDT82P2288 Datasheet PDF : 362 Pages
| |||
IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.24 WAVEFORM SHAPER / LINE BUILD OUT ............................................................................................................................................... 100
3.24.1 Preset Waveform Template ......................................................................................................................................................... 100
3.24.1.1 T1/J1 Mode .................................................................................................................................................................... 100
3.24.1.2 E1 Mode ......................................................................................................................................................................... 101
3.24.2 Line Build Out (LBO) (T1 Only) ................................................................................................................................................... 101
3.24.3 User-Programmable Arbitrary Waveform .................................................................................................................................. 101
3.25 LINE DRIVER ............................................................................................................................................................................................. 109
3.26 TRANSMITTER IMPEDANCE MATCHING ............................................................................................................................................... 109
3.27 TESTING AND DIAGNOSTIC FACILITIES ............................................................................................................................................... 109
3.27.1 PRBS Generator / Detector ......................................................................................................................................................... 109
3.27.1.1 Pattern Generator ........................................................................................................................................................... 110
3.27.1.2 Pattern Detector ............................................................................................................................................................. 110
3.27.2 Loopback ...................................................................................................................................................................................... 111
3.27.2.1 System Loopback ........................................................................................................................................................... 111
3.27.2.2 Payload Loopback .......................................................................................................................................................... 111
3.27.2.3 Local Digital Loopback 1 ................................................................................................................................................ 111
3.27.2.4 Remote Loopback .......................................................................................................................................................... 111
3.27.2.5 Local Digital Loopback 2 ................................................................................................................................................ 111
3.27.2.6 Analog Loopback ............................................................................................................................................................ 111
3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................. 111
3.28 INTERRUPT SUMMARY ............................................................................................................................................................................ 113
4 OPERATION .................................................................................................................................................................. 115
4.1 POWER-ON SEQUENCE ........................................................................................................................................................................... 115
4.2 RESET ........................................................................................................................................................................................................ 115
4.3 RECEIVE / TRANSMIT PATH POWER DOWN ......................................................................................................................................... 115
4.4 MICROPROCESSOR INTERFACE ........................................................................................................................................................... 115
4.4.1 SPI Mode ....................................................................................................................................................................................... 116
4.4.2 Parallel Microprocessor Interface .............................................................................................................................................. 116
4.5 INDIRECT REGISTER ACCESS SCHEME ............................................................................................................................................... 117
4.5.1 Indirect Register Read Access ................................................................................................................................................... 117
4.5.2 Indirect Register Write Access ................................................................................................................................................... 117
5 PROGRAMMING INFORMATION ................................................................................................................................. 118
5.1 REGISTER MAP ......................................................................................................................................................................................... 118
5.1.1 T1/J1 Mode .................................................................................................................................................................................... 118
5.1.1.1 Direct Register ................................................................................................................................................................ 118
5.1.1.2 Indirect Register ............................................................................................................................................................. 125
5.1.2 E1 Mode ........................................................................................................................................................................................ 126
5.1.2.1 Direct Register ................................................................................................................................................................ 126
5.1.2.2 Indirect Register ............................................................................................................................................................. 132
5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 134
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 135
5.2.1.1 Direct Register ................................................................................................................................................................ 135
5.2.1.2 Indirect Register ............................................................................................................................................................. 228
5.2.2 E1 Mode ........................................................................................................................................................................................ 236
5.2.2.1 Direct Register ................................................................................................................................................................ 236
5.2.2.2 Indirect Register ............................................................................................................................................................. 329
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 339
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) .................................................................................................................. 339
6.2 JTAG DATA REGISTER ............................................................................................................................................................................ 340
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 340
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 340
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 340
6.3 TEST ACCESS PORT CONTROLLER ...................................................................................................................................................... 343
Table of Contents
5
March 04, 2009
Share Link: 