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IDT82P2284BB

Quad T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

List of Tables

Table 1: Operating Mode Selection ........................................................................................................................................................................... 14

Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 14

Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 15

Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 16

Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... 17

Table 6: Criteria Of Speed Adjustment Start .............................................................................................................................................................. 18

Table 7: Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... 18

Table 8: Excessive Zero Error Definition ................................................................................................................................................................... 19

Table 9: LOS Condition In T1/J1 Mode ...................................................................................................................................................................... 21

Table 10: LOS Condition In E1 Mode .......................................................................................................................................................................... 21

Table 11: Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... 22

Table 12: The Structure of SF ..................................................................................................................................................................................... 23

Table 13: The Structure of ESF ................................................................................................................................................................................... 24

Table 14: The Structure of T1 DM ............................................................................................................................................................................... 25

Table 15: The Structure of SLC-96 .............................................................................................................................................................................. 26

Table 16: Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ 28

Table 17: Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ 29

Table 18: The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. 33

Table 19: FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ 34

Table 20: Interrupt Source In E1 Frame Processor ..................................................................................................................................................... 36

Table 21: Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ 37

Table 22: Monitored Events In T1/J1 Mode ................................................................................................................................................................. 38

Table 23: Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ 39

Table 24: Monitored Events In E1 Mode ..................................................................................................................................................................... 40

Table 25: Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ 41

Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... 42

Table 27: Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... 43

Table 28: Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... 44

Table 29: Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... 45

Table 30: Interrupt Summarize In HDLC Mode ........................................................................................................................................................... 46

Table 31: Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... 48

Table 32: Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... 49

Table 33: Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... 49

Table 34: Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... 50

Table 35: Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... 52

Table 36: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 53

Table 37: µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 53

Table 38: Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... 54

Table 39: Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... 55

Table 40: Operating Modes Selection In E1 Receive Path .......................................................................................................................................... 60

Table 41: Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... 61

Table 42: Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... 62

Table 43: Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... 67

Table 44: Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... 68

Table 45: Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... 69

Table 46: Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... 71

Table 47: E1 Frame Generation .................................................................................................................................................................................. 72

Table 48: Control Over E Bits ...................................................................................................................................................................................... 72

List of Tables

vi

March 22, 2004

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