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IDT82P2284

Quad T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2284

QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

Type

OSCI

Input

OSCO

CLK_SEL[0]

CLK_SEL[1]

CLK_SEL[2]

Output

Input

CLK_GEN_1.544

CLK_GEN_2.048

REFA_OUT

Output

Output

Output

REFB_OUT

Output

RESET

Input

GPIO[0]

GPIO[1]

Output / Input

THZ

INT

REFR

Input

Output

Output

Pin No.

B13

C13

D15

C14

B15

A16

D14

A15

B14

A14

E13

D13

B16

T11

C16

Description

OSCI: Crystal Oscillator Input

This pin is connected to an external clock source.

The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty

cycle should be from 40% to 60%.

OSCO: Crystal Oscillator Output

This pin outputs the inverted, buffered clock input from OSCI.

CLK_SEL[2:0]: Clock Selection

These three pins select the input clock signal:

When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;

when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.

When the CLK_SEL[1:0] pins are ‘00’, the N is 1;

when the CLK_SEL[1:0] pins are ‘01’, the N is 2;

when the CLK_SEL[1:0] pins are ‘10’, the N is 3;

when the CLK_SEL[1:0] pins are ‘11’, the N is 4.

CLK_SEL[2:0] are Schmitt-trigger inputs.

CLK_GEN_1.544: Clock Generator 1.544 MHz Output

This pin outputs the 1.544 MHz clock signal generated by the Clock Generator.

CLK_GEN_2.048: Clock Generator 2.048 MHz Output

This pin outputs the 2.048 MHz clock signal generated by the Clock Generator.

REFA_OUT: Reference Clock Output A

When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function

block of one of the four links. The link is selected by the RO1[1:0] bits (b1~0, T1/J1-007H / b1~0, E1-007H).

When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-

03EH,... / b0, E1-03EH,...). *

REFB_OUT: Reference Clock Output B

When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function

block of one of the four links. The link is selected by the RO2[1:0] bits (b4~3, T1/J1-007H / b4~3, E1-007H).

When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-

03EH,... / b0, E1-03EH,...). *

Control Interface

RESET: Reset (Active Low)

A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the

reset. The RESET pin is a Schmitt-trigger input with a weak pull-up resistor.

General Purpose I/O [1:0]

These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, T1/J1-006H / b1~0, E1-

006H) respectively. When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, T1/J1-

006H / b3~2, E1-006H) respectively. When the pins are output, their polarities are controlled by the

LEVEL[1:0] bits (b3~2, T1/J1-006H / b3~2, E1-006H) respectively.

GPIO[1:0] are Schmitt-trigger input/output with a pull-up resistor.

THZ: Transmit High-Z

A high level on this pin puts all the TTIPn/TRINGn pins into high impedance state.

THZ is a Schmitt-trigger input.

INT: Interrupt (Active Low)

This is the open drain, active low interrupt output. This pin will stay low until all the active unmasked interrupt

indication bits are cleared.

REFR:

This pin should be connected to ground via an external 10K resistor.

Note:

* This feature is available in ZB revistion only.

Pin Description

7

March 22, 2004

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