IDT82P2284 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82P2284 Datasheet PDF : 384 Pages
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IDT82P2284
2 PIN DESCRIPTION
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
RTIP[1]
RTIP[2]
RTIP[3]
RTIP[4]
RRING[1]
RRING[2]
RRING[3]
RRING[4]
TTIP[1]
TTIP[2]
TTIP[3]
TTIP[4]
TRING[1]
TRING[2]
TRING[3]
TRING[4]
RSD[1] / MRSDA[1]
RSD[2] / MRSDB[1]
RSD[3]
RSD[4]
Input
Output
High-Z
Output
RSIG[1] / MRSIGA[1]
RSIG[2] / MRSIGB[1]
RSIG[3]
RSIG[4]
High-Z
Output
Pin No.
C11
D8
D6
B4
D11
D9
D5
C4
A12
A8
A7
A1
A11
A9
A6
A2
P3
R2
T1
P1
T2
P2
R1
N3
Description
Line and System Interface
RTIP[1:4] / RRING[1:4]: Receive Bipolar Tip/Ring for Link 1 ~ 4
These pins are the differential line receiver inputs.
TTIP[1:4] / TRING[1:4]: Transmit Bipolar Tip/Ring for Link 1 ~ 4
These pins are the differential line driver outputs and can be set to high impedance state globally or individu-
ally. A logic high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-
023H,... / b4, E1-023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high
impedance state.
Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line
Driver for details).
RSD[1:4]: Receive Side System Data for Link 1 ~ 4
The processed data stream is output on these pins.
In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins
are updated on the active edge of the corresponding RSCKn or all four RSDn pins are updated on the active
edge of RSCK[1].
MRSDA[1] / MRSDB[1]: Multiplexed Receive Side System Data A / B for Link 1 ~ 4
In Receive Multiplexed mode, the MRSDA[1] pin or the MRSDB[1] pin is used to output the processed data
stream. Using a byte-interleaved multiplexing scheme, the MRSDA[1]/MRSDB[1] pins output the data from
Link 1 to Link 4. The data on the MRSDA[1]/MRSDB[1] pin is updated on the active edge of the MRSCK. The
data on MRSDA[1] is the same as the data on MRSDB[1]. MRSDB[1] is for back-up purpose.
RSIG[1:4]: Receive Side System Signaling for Link 1 ~ 4
The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are
channel/timeslot-aligned with the data output on the corresponding RSDn pin.
In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins
are updated on the active edge of the corresponding RSCKn or all four RSIGn are updated on the active edge
of RSCK[1].
MRSIGA[1] / MRSIGB[1]: Multiplexed Receive Side System Signaling A / B for Link 1 ~ 4
In Receive Multiplexed mode, the MRSIGA[1] pin or the MRSIGB[1] pin is used to output the extracted signal-
ing bits. The signaling bits are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the
data output on the corresponding MRSDA[1]/MRSDB[1] pins. Using the byte-interleaved multiplexing
scheme, the MRSIGA[1]/MRSIGB[1] pins output the signaling bits from Link 1 to Link 4. The signaling bits on
the MRSIGA[1]/MRSIGB[1] pin is updated on the active edge of the MRSCK. The signaling bits on
MRSIGA[1] is the same as the signaling bits on MRSIGB[1]. MRSIGB[1] is for back-up purpose.
Note:
* The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘,...’ is followed, this bit is in a per-link control reg-
ister and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.
Pin Description
4
March 22, 2004
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