IDT82P2282 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82P2282 Datasheet PDF : 383 Pages
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.27.2.6 Analog Loopback .............................................................................................................................................................. 91
3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................... 91
3.28 INTERRUPT SUMMARY .............................................................................................................................................................................. 94
4 OPERATION .................................................................................................................................................................... 95
4.1 POWER-ON SEQUENCE ............................................................................................................................................................................. 95
4.2 RESET .......................................................................................................................................................................................................... 95
4.3 RECEIVE / TRANSMIT PATH POWER DOWN ........................................................................................................................................... 95
4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................. 96
4.4.1 SPI Mode ......................................................................................................................................................................................... 96
4.4.2 Parallel Microprocessor Interface ................................................................................................................................................ 97
4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................. 98
4.5.1 Indirect Register Read Access ..................................................................................................................................................... 98
4.5.2 Indirect Register Write Access ..................................................................................................................................................... 98
5 PROGRAMMING INFORMATION ................................................................................................................................... 99
5.1 REGISTER MAP ........................................................................................................................................................................................... 99
5.1.1 T1/J1 Mode ...................................................................................................................................................................................... 99
5.1.1.1 Direct Register .................................................................................................................................................................. 99
5.1.1.2 Indirect Register ............................................................................................................................................................. 104
5.1.2 E1 Mode ........................................................................................................................................................................................ 105
5.1.2.1 Direct Register ................................................................................................................................................................ 105
5.1.2.2 Indirect Register ............................................................................................................................................................. 110
5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 112
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 113
5.2.1.1 Direct Register ................................................................................................................................................................ 113
5.2.1.2 Indirect Register ............................................................................................................................................................. 215
5.2.2 E1 Mode ........................................................................................................................................................................................ 228
5.2.2.1 Direct Register ................................................................................................................................................................ 228
5.2.2.2 Indirect Register ............................................................................................................................................................. 331
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 346
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) .................................................................................................................. 347
6.2 JTAG DATA REGISTER ............................................................................................................................................................................ 348
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 348
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 348
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 348
6.3 TEST ACCESS PORT CONTROLLER ...................................................................................................................................................... 350
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 354
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 354
7.2 RECOMMENDED OPERATING CONDITIONS ......................................................................................................................................... 354
7.3 D.C. CHARACTERISTICS ......................................................................................................................................................................... 355
7.4 DIGITAL I/O TIMING CHARACTERISTICS ............................................................................................................................................... 356
7.4.1 In Non-Multiplexed Mode ............................................................................................................................................................. 356
7.4.2 In Multiplexed Mode ..................................................................................................................................................................... 357
7.5 CLOCK FREQUENCY REQUIREMENT .................................................................................................................................................... 357
7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................... 358
7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................................................ 359
7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................ 360
7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................ 361
7.10 JITTER TOLERANCE ................................................................................................................................................................................ 362
7.10.1 T1/J1 Mode .................................................................................................................................................................................... 362
7.10.2 E1 Mode ........................................................................................................................................................................................ 363
7.11 JITTER TRANSFER ................................................................................................................................................................................... 364
7.11.1 T1/J1 Mode .................................................................................................................................................................................... 364
7.11.2 E1 Mode ........................................................................................................................................................................................ 365
Table of Contents
iv
October 7, 2003
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