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IDT82P2282

Dual T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2282

DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

OSCO

CLK_SEL[0]

CLK_SEL[1]

CLK_SEL[2]

CLK_GEN

REFA_OUT

REFB_OUT

RESET

GPIO

THZ

INT

REFR

CS

Type Pin No.

Description

Output

Input

Output

Output

Output

94 OSCO: Crystal Oscillator Output

This pin outputs the inverted, buffered clock input from OSCI.

85 CLK_SEL[2:0]: Clock Selection

86 These three pins select the input clock signal:

87 When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;

when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.

When the CLK_SEL[1:0] pins are ‘00’, the N is 1;

when the CLK_SEL[1:0] pins are ‘01’, the N is 2;

when the CLK_SEL[1:0] pins are ‘10’, the N is 3;

when the CLK_SEL[1:0] pins are ‘11’, the N is 4.

CLK_SEL[2:0] are Schmitt-trigger inputs.

81 CLK_GEN: Clock Generator

This pin outputs the 1.544/2.048 MHz clock signal generated by the Clock Generator.

90 REFA_OUT: Reference Clock Output A

This pin outputs a recovered clock from the Clock and Data Recovery function block of one of the two links. The link is

selected by the RO10 bit (b0, T1/J1-007H / b0, E1-007H).

92 REFB_OUT: Reference Clock Output B

This pin outputs a recovered clock from the Clock and Data Recovery function block of one of the two links. The link is

selected by the RO20 bit (b3, T1/J1-007H / b3, E1-007H).

Control Interface

Input

84 RESET: Reset (Active Low)

A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.

Reset can only be applied when the clock on the OSCI pin is available.

The RESET pin is a Schmitt-trigger input with a weak pull-up resistor.

Output / Input 1 General Purpose I/O

This pin can be defined as input pin or output pin by the DIR0 bit (b0, T1/J1-006H / b0, E1-006H). When the pin is

input, its polarity is indicated by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H). When the pin is output, its polarity is

controlled by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H).

GPIO is a Schmitt-trigger input/output with a pull-up resistor.

Input

Output

2 THZ: Transmit High-Z

A high level on this pin puts all the TTIPn/TRINGn pins into high impedance state.

THZ is a Schmitt-trigger input.

49 INT: Interrupt (Active Low)

This is the open drain, active low interrupt output. This pin will stay low until all the active unmasked interrupt indication

bits are cleared.

Output

9 REFR:

This pin should be connected to ground via an external 10K resistor.

Input

48 CS: Chip Select (Active Low)

This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least once

after power up to clear the internal test modes. A transition from high to low must occur on this pin for each Read/Write

operation and can not return to high until the operation is completed.

CS is a Schmitt-trigger input.

Pin Description

7

October 7, 2003

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