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IDT82P2282

Dual T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2282

2 PIN DESCRIPTION

DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

RTIP[1]

RTIP[2]

RRING[1]

RRING[2]

TTIP[1]

TTIP[2]

TRING[1]

TRING[2]

RSD[1] / MRSD

RSD[2]

RSIG[1] / MRSIG

RSIG[2]

Type

Input

Output

Output

Output

Pin No.

Description

Line and System Interface

27 RTIP[1:2] / RRING[1:2]: Receive Bipolar Tip/Ring for Link 1 ~ 2

12 These pins are the differential line receiver inputs.

28

11

21 TTIP[1:2] / TRING[1:2]: Transmit Bipolar Tip/Ring for Link 1 ~ 2

18 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic

high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-023H,... / b4, E1-

22 023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high impedance state.

17 Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line Driver for

details).

79 RSD[1:2]: Receive Side System Data for Link 1 ~ 2

71 The processed data stream is output on these pins.

In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.

In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins are

updated on the active edge of the corresponding RSCKn or both two RSDn pins are updated on the active edge of

RSCK[1].

MRSD: Multiplexed Receive Side System Data for Link 1 ~ 2

In Receive Multiplexed mode, the MRSD pin is used to output the processed data stream. Using a byte-interleaved

multiplexing scheme, the MRSD pin outputs the data from Link 1 and Link 2. The data on the MRSD pin is updated on

the active edge of the MRSCK.

78 RSIG[1:2]: Receive Side System Signaling for Link 1 ~ 2

70 The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/

timeslot-aligned with the data output on the corresponding RSDn pin.

In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.

In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins are

updated on the active edge of the corresponding RSCKn or both two RSIGn are updated on the active edge of

RSCK[1].

MRSIG: Multiplexed Receive Side System Signaling for Link 1 ~ 2

In Receive Multiplexed mode, the MRSIG pin is used to output the extracted signaling bits. The signaling bits are

located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data output on the MRSD pin. Using the

byte-interleaved multiplexing scheme, the MRSIG pin outputs the signaling bits from Link 1 and Link 2. The signaling

bits on the MRSIG pin is updated on the active edge of the MRSCK.

Note:

* The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘,...’ is followed, this bit is in a per-link control reg-

ister and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.

Pin Description

4

October 7, 2003

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