IDT82P2282(2009) Просмотр технического описания (PDF) - Integrated Device Technology

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производитель

IDT82P2282
(Rev.:2009)

Dual T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

List of Tables

Table 1: Operating Mode Selection ........................................................................................................................................................................... 24

Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 24

Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 25

Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 27

Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... 28

Table 6: Criteria Of Speed Adjustment Start .............................................................................................................................................................. 29

Table 7: Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... 29

Table 8: Excessive Zero Error Definition ................................................................................................................................................................... 30

Table 9: LOS Condition In T1/J1 Mode ...................................................................................................................................................................... 32

Table 10: LOS Condition In E1 Mode .......................................................................................................................................................................... 32

Table 11: Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... 33

Table 12: The Structure of SF ..................................................................................................................................................................................... 34

Table 13: The Structure of ESF ................................................................................................................................................................................... 35

Table 14: The Structure of T1 DM ............................................................................................................................................................................... 36

Table 15: The Structure of SLC-96 .............................................................................................................................................................................. 37

Table 16: Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ 39

Table 17: Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ 40

Table 18: The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. 44

Table 19: FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ 45

Table 20: Interrupt Source In E1 Frame Processor ..................................................................................................................................................... 47

Table 21: Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ 48

Table 22: Monitored Events In T1/J1 Mode ................................................................................................................................................................. 49

Table 23: Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ 50

Table 24: Monitored Events In E1 Mode ..................................................................................................................................................................... 51

Table 25: Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ 52

Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... 53

Table 27: Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... 54

Table 28: Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... 55

Table 29: Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... 56

Table 30: Interrupt Summarize In HDLC Mode ........................................................................................................................................................... 57

Table 31: Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... 58

Table 32: Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... 59

Table 33: Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... 59

Table 34: Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... 60

Table 35: Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... 62

Table 36: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 63

Table 37: µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 63

Table 38: Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... 64

Table 39: Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... 65

Table 40: Operating Modes Selection In E1 Receive Path .......................................................................................................................................... 70

Table 41: Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... 72

Table 42: Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... 73

Table 43: Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... 79

Table 44: Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... 80

Table 45: Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... 81

Table 46: Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... 83

Table 47: E1 Frame Generation .................................................................................................................................................................................. 84

Table 48: Control Over E Bits ...................................................................................................................................................................................... 84

List of Tables

8

August 20, 2009

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