IDT82P2281 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82P2281 Datasheet PDF : 375 Pages
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.27.2.6 Analog Loopback .............................................................................................................................................................. 91
3.28 INTERRUPT SUMMARY .............................................................................................................................................................................. 92
4 OPERATION .................................................................................................................................................................... 93
4.1 POWER-ON SEQUENCE ............................................................................................................................................................................. 93
4.2 RESET .......................................................................................................................................................................................................... 93
4.3 RECEIVE / TRANSMIT PATH POWER DOWN ........................................................................................................................................... 93
4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................. 94
4.4.1 SPI Mode ......................................................................................................................................................................................... 94
4.4.2 Parallel Microprocessor Interface ................................................................................................................................................ 95
4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................. 96
4.5.1 Indirect Register Read Access ..................................................................................................................................................... 96
4.5.2 Indirect Register Write Access ..................................................................................................................................................... 96
5 PROGRAMMING INFORMATION ................................................................................................................................... 97
5.1 REGISTER MAP ........................................................................................................................................................................................... 97
5.1.1 T1/J1 Mode ...................................................................................................................................................................................... 97
5.1.1.1 Direct Register .................................................................................................................................................................. 97
5.1.1.2 Indirect Register ............................................................................................................................................................. 102
5.1.2 E1 Mode ........................................................................................................................................................................................ 103
5.1.2.1 Direct Register ................................................................................................................................................................ 103
5.1.2.2 Indirect Register ............................................................................................................................................................. 108
5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 110
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 111
5.2.1.1 Direct Register ................................................................................................................................................................ 111
5.2.1.2 Indirect Register ............................................................................................................................................................. 210
5.2.2 E1 Mode ........................................................................................................................................................................................ 223
5.2.2.1 Direct Register ................................................................................................................................................................ 223
5.2.2.2 Indirect Register ............................................................................................................................................................. 323
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 338
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) .................................................................................................................. 339
6.2 JTAG DATA REGISTER ............................................................................................................................................................................ 340
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 340
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 340
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 340
6.3 TEST ACCESS PORT CONTROLLER ...................................................................................................................................................... 342
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 346
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 346
7.2 RECOMMENDED OPERATING CONDITIONS ......................................................................................................................................... 346
7.3 D.C. CHARACTERISTICS ......................................................................................................................................................................... 347
7.4 DIGITAL I/O TIMING CHARACTERISTICS ............................................................................................................................................... 348
7.4.1 In Non-Multiplexed Mode ............................................................................................................................................................. 348
7.4.2 In Multiplexed Mode ..................................................................................................................................................................... 349
7.5 CLOCK FREQUENCY REQUIREMENT .................................................................................................................................................... 349
7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................... 350
7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................................................ 351
7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................ 352
7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................ 353
7.10 JITTER TOLERANCE ................................................................................................................................................................................ 354
7.10.1 T1/J1 Mode .................................................................................................................................................................................... 354
7.10.2 E1 Mode ........................................................................................................................................................................................ 355
7.11 JITTER TRANSFER ................................................................................................................................................................................... 356
7.11.1 T1/J1 Mode .................................................................................................................................................................................... 356
7.11.2 E1 Mode ........................................................................................................................................................................................ 357
7.12 MICROPROCESSOR TIMING SPECIFICATION ....................................................................................................................................... 358
Table of Contents
iv
October 7, 2003
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