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IDT82P2281

Single T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

List of Figures

Figure 1. 80-Pin TQFP (Top View) ................................................................................................................................................................................ 3

Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 13

Figure 3. Monitoring Receive Path .............................................................................................................................................................................. 14

Figure 4. Monitoring Transmit Path ............................................................................................................................................................................. 14

Figure 5. Jitter Attenuator ............................................................................................................................................................................................ 16

Figure 6. AMI Bipolar Violation Error ........................................................................................................................................................................... 18

Figure 7. B8ZS Excessive Zero Error ......................................................................................................................................................................... 18

Figure 8. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................. 18

Figure 9. E1 Frame Searching Process ...................................................................................................................................................................... 29

Figure 10. Basic Frame Searching Process ................................................................................................................................................................ 30

Figure 11. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 32

Figure 12. Standard HDLC Packet .............................................................................................................................................................................. 43

Figure 13. Overhead Indication In The FIFO ............................................................................................................................................................... 44

Figure 14. Standard SS7 Packet ................................................................................................................................................................................. 45

Figure 15. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 49

Figure 16. Signaling Output In E1 Mode ...................................................................................................................................................................... 49

Figure 17. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 54

Figure 18. T1/J1 To E1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 54

Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 55

Figure 20. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 56

Figure 21. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 56

Figure 22. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 57

Figure 23. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 57

Figure 24. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 61

Figure 25. E1 To T1/J1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 61

Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 62

Figure 27. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 63

Figure 28. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 63

Figure 29. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 64

Figure 30. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 64

Figure 31. DSX-1 Waveform Template ........................................................................................................................................................................ 79

Figure 32. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 79

Figure 33. E1 Waveform Template .............................................................................................................................................................................. 79

Figure 34. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 79

Figure 35. Hardware Reset When Powered-Up .......................................................................................................................................................... 93

Figure 36. Hardware Reset In Normal Operation ........................................................................................................................................................ 93

Figure 37. Read Operation In SPI Mode ..................................................................................................................................................................... 94

Figure 38. Write Operation In SPI Mode ...................................................................................................................................................................... 94

Figure 39. JTAG Architecture .................................................................................................................................................................................... 338

Figure 40. JTAG State Diagram ................................................................................................................................................................................ 344

Figure 41. I/O Timing in Non-Multiplexed Mode ........................................................................................................................................................ 348

Figure 42. I/O Timing in Multiplexed Mode ................................................................................................................................................................ 349

Figure 43. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 354

Figure 44. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 355

Figure 45. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 356

Figure 46. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 357

Figure 47. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 358

Figure 48. Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... 359

List of Figures

viii

October 7, 2003

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