IDTCV125 Просмотр технического описания (PDF) - Integrated Device Technology
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IDTCV125 Datasheet PDF : 24 Pages
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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 6
Bit
Output(s) Affected
Description / Function
0
1
Type
0
CPU[2:0]
FSA latched value on power up
R
1
CPU[2:0]
FSB latched value on power up
R
2
CPU[2:0]
FSC latched value on power up
R
3
PCI, SRC
Software PCI_STOP control for Stop all PCI, PCIF, and Software STOP
RW
PCI and SRC CLK
SRC which can be stopped
Disabled
by PCI_STOP#
4
REF
REF drive strength
1x drive
2x drive
RW
5
Reserved
RW
6
Test clock mode entry control
Normal operation
Test mode, controlled
RW
by Byte 6, Bit 7
7
CPU, SRC, PCI
Only valid when Byte 6, Bit 6
Hi-Z
PCIF, REF,
is HIGH
USB48, DOT96
REF/N
RW
Power On
1
1
0
0
0
BYTE 7
Bit
Output(s) Affected
Description / Function
0
0
Vendor ID
1
Vendor ID
2
Vendor ID
3
Vendor ID
4
Revision ID
5
Revision ID
6
Revision ID
7
Revision ID
1
Type
Power On
R
1
R
0
R
1
R
0
R
0
R
0
R
0
R
0
BYTE 8, LVDS CONTROL BYTE
Bit
Output(s) Affected
Description/Function
0
1
Type
0
LVDS
HW/ SMBus control
HW(1)
SW
RW
1
LVDS SSC EN
Spread spectrum enable
Off
On
RW
2
LVDS Enable
Output Enable
Disable
Enable
RW
3
SEL 100/96#
Select LVDS frequency
96MHz
100MHZ
RW
4
S3
see SSC table
RW
5
S2
see SSC table
RW
6
S1
see SSC table
RW
7
S0
see SSC table
RW
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
Power On
0
1
1
SEL 100/96#
0
0
0
0
8
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