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IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

BYTE 13

Bit

Output(s) Affected

Description / Function

0

0

48MHzStr0

1

48MHStr1

USB48MHz0 strength selection

2

REFStr0

3

REFStr1

REF strength selection

4

PCIStrC0

5

PCIStrC1

PCI strength selection

6

PCIFStr0

7

PCIFStr1

PCIF strength selection

COMMERCIAL TEMPERATURE RANGE

1

Type

Power On

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

3.3V ± 5%

3.3V ± 5%

2

—

VDD + 0.3

V

VSS - 0.3

—

0.8

V

VIH_FS

VIL_FS

IIH

IIL1

LOW Voltage, HIGH Threshold

LOW Voltage, LOW Threshold

Input HIGH Current

Input LOW Current

For FSA.B.C test_mode

For FSA.B.C test_mode

VIN = VDD

VIN = 0V, inputs with no pull-up resistors

0.7

—

VDD + 0.3

V

VSS - 0.3

—

0.35

V

–5

—

5

µA

–5

—

—

µA

IIL2

Input LOW Current

VIN = 0V, inputs with pull-up resistors

–200

—

—

µA

IDD3.3OP

IDD3.3PD

Operating Supply Current

Powerdown Current

FI

Input Frequency(1)

LPIN

Pin Inductance(2)

Full active, CL = full load

All differential pairs driven

All differential pairs tri-stated

VDD = 3.3V

—

—

400

mA

—

—

70

mA

—

—

12

— 14.31818

—

MHz

—

—

7

nH

CIN

COUT

CINX

Input Capacitance(2)

Logic inputs

Output pin capacitance

XTAL_IN

—

—

5

—

—

6

pF

—

—

5

COUTX

TSTAB

Clock Stabilization(2,3)

Modulation Frequency(2)

TDRIVE_SRC(2)

TDRIVE_PD(2)

TFALL_PD(2)

TRISE_PD(3)

TDRIVE_CPU_STOP#(2)

TFALL_CPU_STOP#(2)

TRISE_CPU_STOP#(3)

XTAL_OUT

From VDD power-up or de-assertion of PD to first clock

Triangular modulation

SRC output enable after PCI_STOP# de-assertion

CPU output enable after PD de-assertion

Fall time of PD

Rise time of PD

CPU output enable after CPU_STOP# de-assertion

Fall time of CPU_STOP#

Rise time of CPU_STOP#

—

—

12

—

—

1.8

ms

30

—

33

KHz

—

—

15

ns

—

—

300

us

—

—

5

ns

—

—

5

ns

—

—

10

us

—

—

5

ns

—

—

5

ns

NOTES:

1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.

2. This parameter is guaranteed by design, but not 100% production tested.

3. See TIMING DIAGRAMS for timing requirements.

10

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