IDT82V2082 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82V2082
Integrated Device Technology
IDT82V2082 Datasheet PDF : 88 Pages
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IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.8.2 DIGITAL LOOPBACK ............................................................................................. 35
3.8.3 REMOTE LOOPBACK............................................................................................ 36
3.8.4 INBAND LOOPBACK.............................................................................................. 37
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 37
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 37
3.8.4.3 Automatic Remote Loopback .................................................................. 38
3.9 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 39
3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 39
3.9.2 ERROR DETECTION AND COUNTING ................................................................ 39
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 40
3.10 LINE DRIVER FAILURE MONITORING ........................................................................... 40
3.11 MCLK AND TCLK ............................................................................................................. 41
3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 41
3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 41
3.12 MICROCONTROLLER INTERFACES ............................................................................. 42
3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 42
3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 42
3.13 INTERRUPT HANDLING .................................................................................................. 43
3.14 5V TOLERANT I/O PINS .................................................................................................. 44
3.15 RESET OPERATION ........................................................................................................ 44
3.16 POWER SUPPLY ............................................................................................................. 44
4 PROGRAMMING INFORMATION .............................................................................................. 45
4.1 REGISTER LIST AND MAP ............................................................................................. 45
4.2 Reserved Registers .......................................................................................................... 45
4.3 REGISTER DESCRIPTION .............................................................................................. 47
4.3.1 GLOBAL REGISTERS............................................................................................ 47
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 48
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 48
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 49
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 51
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 53
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 56
4.3.8 LINE STATUS REGISTERS ................................................................................... 59
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 62
4.3.10 COUNTER REGISTERS ........................................................................................ 63
5 HARDWARE CONTROL PIN SUMMARY .................................................................................. 64
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 66
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 67
6.2 JTAG DATA REGISTER ................................................................................................... 67
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 67
6.2.2 BYPASS REGISTER (BR)...................................................................................... 67
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May 4, 2009
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