IDT82V2081 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT82V2081

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

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TEMPERATURE RANGES

3.9 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 29

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 29

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30

3.10 LINE DRIVER FAILURE MONITORING ........................................................................... 30

3.11 MCLK AND TCLK ............................................................................................................. 31

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 31

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 31

3.12 MICROCONTROLLER INTERFACES ............................................................................. 32

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32

3.13 INTERRUPT HANDLING .................................................................................................. 33

3.14 5V TOLERANT I/O PINS .................................................................................................. 33

3.15 RESET OPERATION ........................................................................................................ 33

3.16 POWER SUPPLY ............................................................................................................. 33

4 PROGRAMMING INFORMATION .............................................................................................. 34

4.1 REGISTER LIST AND MAP ............................................................................................. 34

4.2 REGISTER DESCRIPTION .............................................................................................. 35

4.2.1 CONTROL REGISTERS......................................................................................... 35

4.2.2 TRANSMIT PATH CONTROL REGISTERS........................................................... 36

4.2.3 RECEIVE PATH CONTROL REGISTERS ............................................................. 38

4.2.4 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 40

4.2.5 INTERRUPT CONTROL REGISTERS ................................................................... 43

4.2.6 LINE STATUS REGISTERS ................................................................................... 46

4.2.7 INTERRUPT STATUS REGISTERS ...................................................................... 48

4.2.8 COUNTER REGISTERS ........................................................................................ 49

5 HARDWARE CONTROL PIN SUMMARY .................................................................................. 50

6 TEST SPECIFICATIONS ............................................................................................................ 52

7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 63

7.1 SERIAL INTERFACE TIMING .......................................................................................... 63

7.2 PARALLEL INTERFACE TIMING ..................................................................................... 64

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