IDT82V2044 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

производитель

IDT82V2044

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2044

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

RCLK0

RCLK1

RCLK2

RCLK3

MCLK

Type

O

High-Z

I

Pin No.

TQFP144 PBGA160

Description

RCLKn: Receive Clock for Channel 0~3

39

32

78

71

P1

M1

M14

P14

In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn. The

received data are clocked out of the device on the rising edges of RCLKn if pin CLKE is high, or on falling

edges of RCLKn if pin CLKE is low.

In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with

RDPn and RDNn. The clock is recovered from the signal on RCLKn.

If Receiver n is powered down, the corresponding RCLKn is in high-Z.

MCLK: Master Clock

This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz

(for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.

In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse (Data

10

E1 Recovery mode). When MCLK is low, all the receivers are powered down, and the output pins RCLKn,

RDPn and RDNn are switched to high-Z.

In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin

description for details).

NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided.

LOS0

LOS1

LOS2

LOS3

42

O

35

75

68

I

MODE2

(Pulled to

11

VDDIO/2)

K4 LOSn: Loss of Signal Output for Channel 0~3

K3 A high level on this pin indicates the loss of signal when there is no transition over a specified period of

K12 time or no enough ones density in the received signal. The transition will return to low automatically when

K11 there is enough transitions over a specified period of time with a certain ones density in the received sig-

nal. The LOS assertion and desertion criteria are described in 2.4.4 Loss of Signal (LOS) Detection.

Hardware/Host Control Interface

MODE2: Control Mode Select 2

The signal on this pin determines which control mode is selected to control the device:

MODE2

Low

VDDIO/2

High

Control Interface

Hardware Mode

Serial Host Interface

Parallel Host Interface

Hardware control pins include MODE[2:0], TS[2:0], LP[3:0], CODE, CLKE, JAS and OE.

E2

Serial host Interface pins include CS, SCLK, SDI, SDO and INT.

Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The

device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions

below for details):

MODE[2:0]

100

101

110

111

Host Interface

Non-multiplexed Motorola Interface

Non-multiplexed Intel Interface

Multiplexed Motorola Interface

Multiplexed Intel Interface

MODE1: Control Mode Select 1

MODE1

I

43

K2

In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin

is low, and operates with multiplexed address and data bus when this pin is high.

In serial host mode or hardware mode, this pin should be grounded.

Pin Description

6

September 22, 2005

Share Link: