IDT82V2044 Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
производитель
IDT82V2044 Datasheet PDF : 61 Pages
| |||
IDT82V2044
1 PIN DESCRIPTION
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description
Name
Type
TTIP0
TTIP1
TTIP2
TTIP3
TRING0
TRING1
TRING2
TRING3
RTIP0
RTIP1
RTIP2
RTIP3
RRING0
RRING1
RRING2
RRING3
Analog
Output
Analog
Input
Pin No.
TQFP144 PBGA160
Description
Transmit and Receive Line Interface
45
N5
52
L5
57
64
L10
N10
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~3
These pins are the differential line driver outputs. They will be in high-Z state if pin OE is low or the corre-
46
51
P5
M5
sponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host
mode, each pin can be in high-Z by programming a ‘1’ to the corresponding bit in register OE(1).
58
M10
63
P10
48
P7
55
M7
60
M8
67
P8
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~3
49
N7
These pins are the differential line receiver inputs.
54
L7
61
L8
66
N8
Transmit and Receive Digital Data Interface
TDn: Transmit Data for Channel 0~3
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
I
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVIn: Bipolar Violation Insertion for Channel 0~3
37
30
80
N2
L2
L13
Bipolar violation insertion is available in Single Rail mode 2 (see Table-2 on page 13 and Table-3 on page
14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
73
N13 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~3
38
31
79
N3
L3
L12
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
72
N12
TDPn
TDNn
Output Pulse
0
0
Space
0
1
Negative Pulse
1
0
Positive Pulse
1
1
Space
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see Table-2 on page 13 and Table-3 on page 14).
1. Register name is indicated by bold capital letter. For example, OE indicates Output Enable Register.
Pin Description
4
September 22, 2005
Share Link: 