IDT7M1002S30G Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7M1002S30G Datasheet PDF : 12 Pages
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IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT CYCLE(1)
ADDR "A"
CE "A"
tAS (3)
tWC
INTERRUPT SET ADDRESS (2)
tWR (4)
R/W 1"A"
INT "B"
ADDR "B"
CE "B"
tINS (3)
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS(2)
2795 drw 16
OE "B"
tINR (3)
INT "B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
2795 drw 17
TRUTH TABLE I: Non-Contention Read/Write Control(1)
Inputs
CS
R/W
OE
SEM
H
X
X
H
L
L
X
H
L
H
L
H
X
X
H
X
NOTE:
1. The conditions for non-contention are L_A (0–13) ≠ R_A (0–13).
2.
denotes a LOW to HIGH waveform transition.
TRUTH TABLE II: Semaphore Read/Write Control
Inputs(2)
CS
R/W
OE
SEM
H
H
L
L
H
X
L
L
X
X
L
Outputs
I/O
High-Z
Data_In
Data_OUT
High-Z
Outputs
I/O
Data_OUT
Data_IN
—
Mode
Description
Deselected or Power Down
Write
Read
Outputs Disabled
2795 tbl 13
Mode
Description
Read Data in Semaphore Flag
Write Data_IN (0, 8, 16, 24)
Not Allowed
2795 tbl 14
7.02
11
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